htot
commented
6 years ago I tested this on x86_32. Now retested this on x86_64 and it disappointingly doesn't work at all. I need to go back to to x86_32 to figure out why it worked or seemed to work.
In the mean time, don't spend time here. I'll close this for now.
Hi Andy, here is what I have working now. I don't expect you to merge this yet. Although it works, it is still a hack enabled on ttyS1 only. But it is a big improvement, allowing 4Mb/s even while loading the kernel (I used iperf3 over usb->eth converter). But, I would like to here your comments and make it perfect, maybe eventually you could upstream this.
The 1st (linear buffer for transmit) you've seen before. The 2nd silences the hsu dma interrupt storm. The 3rd makes rx dma setup prior to reception instead of on interrupt of reception of first char. At 2Mb/s the interrupt latency was to large for the FIFO length (on x86_64 at least), even without load.
The hack is of course I enabled this only on ttyS1. For some reason it breaks ttyS0 and ttyS2 if I enable on all. I think on the console ttyS0 dma is not enabled and ttyS2 is maybe a serdev and initialized different?