Closed htot closed 3 years ago
And title for the commit has to be dmaengine: hsu: ...
6043c32 should be OK now
@htot the title prefix seems not addressed.
Hi @andy-shev yes, sorry I only saw your comment on the title after sending to patch to lkml. I guess I will need to fix the title in v2.
As it is now in upstream I close this one.
On Intel Tangier B0 and Anniedale the interrupt line, disregarding to have different numbers, is shared between HSU DMA and UART IPs. Thus on such SoCs we are expecting that IRQ handler is called in UART driver only. hsu_pci_irq was handling the spurious interrupt from HSU DMA by returning immediately. This wastes CPU time and since HSU DMA and HSU UART interrupt occur simultaneously they race to be handled causing delay to the HSU UART interrupt handling. Fix this by disabling the interrupt entirely.
Fixes: 4831e0d9054c ("serial: 8250_mid: handle interrupt correctly in DMA case") Signed-off-by: Ferry Toth ftoth@exalondelft.nl