htot
commented
2 years ago With these patches you can transmit at 3.5Mb/s without loosing chars. You can test this by setting up a pppd between 2 Edisons.
Note: We need to prevent the dma controller from entering a sleep state as waking up can take a long time and the latency can easily be longer then the UART FIFO length (at > 500kb/s). To do this we need to write 0 to /dev/cpu_dma_latency. One way to do this without coding is to run cyclictest in the background:
cyclictest > /dev/null &
andy-shev
All 3 patches have one goal: to minimize chance of loosing char's of a incoming message.
The main reason of loosing char's is the RX interrupt latency. To prevent this, we use DMA for RX but we make sure dma is armed before 1st char arrives (in current kernel 1st char triggers interrupt, which sets up dma). Instead, after RX dma completes we arm dma again for the next message.
Of course the above works only when at the end of a message there is a little time to handle dma interrupt and arm again. This is in practice always the case, except when a single message gets split into 2 parts.
This happens unintentionally in 2 cases: when the circular transmit buffer wraps around and when messages longer then 2k are sent (while the message length is < 1 page). In both cases an interchar gap can occur. When this gap > 5 char lengths on the receiving side dma will terminate possibly leaving not enough time to handle the dma and set up new.
To handle the first case we put both parts of the message on a sgl. To handle the second case, when using DMA we prevent splitting transmit.