General SPI improvements

[andysworkshop]

• The default FIFO notify configuration on the F0 should be quarter-full (1 byte) so that the examples work out of the box on the F0 without the user having to know about the configurable F0 FIFO notification size.
• Better support for 3-Wire SPI. In this mode master MISO and slave MOSI are free for GPIO. We should not initialise them for SPI AFIO in the pin initialisers. I'll also add support for switching SPI direction in the 3-wire mode.