Open PythonLinks opened 1 year ago
I like the way you approach the project. Full of energy! Am totally agree with your comment. Test benches are a necessity. Probably not published but I'm sure there are. Do ask Don or Demitri for them. Along the same line, I've suggested the team to partition the code into modules so that it is easier to validate as well.
I am curious what modules you would define?
As for firing up a simulated outer interpreter, basically being able to interact with a Forth shell running on this simulated CPU, I think I know better how to do that. There are a number of Forth CPUs that have done this. i just have to find the code that does it. Can anyone point me to the right place?
So this chip is looking increasingly interesting. And I am starting to understand it better. Right now my attention is on the Compiler branch, Altera version, because that looks the most recent. It has some verilog for UART TX, and SPI, but no testing software. How did he get it to work, without some software to test it?
In general, it would be great to have more testing/verification software. Particularly because FPGA's are so slow to synthesize, it makes a lot more sense to put energy into the testing software. More efficient to test in simulation than on the fpga itself.
Of great interest to me is to actually fire up the outer interpreter in a shell window, then I have what I need to execute code, and make sure the device runs correctly as I make modifications.
So could you be so kind as to post some of your testing software? Even if not perfect, much easier for me to clean it up, than to write it myself.