The vision of this group is to create a Forth based AI Computer where you can communicate with the system using an English conversational approach. We will add many high level Words for string manipulation, arrays, and other structures as we develop this computer. We will extend Forth to include AI words too. All of this will be built into FPGAs which are really parallel computers written in Behavioral System Verilog (the Assembler).
First compliments on the README. Makes your repository look way way better.
I am interested in running say 8 cores. Ideally that would mean 8 different groups of memory. There is memory on the chip and memory on the board. Can I divide the chip memory into 8 blocks? Can I divide the board memory into 8 blocks. or will different cpus accessing the memories, conflict with each other?
First compliments on the README. Makes your repository look way way better.
I am interested in running say 8 cores. Ideally that would mean 8 different groups of memory. There is memory on the chip and memory on the board. Can I divide the chip memory into 8 blocks? Can I divide the board memory into 8 blocks. or will different cpus accessing the memories, conflict with each other?
Thanks.