SUB(.B),SUBC(.B),CMP(.B)
V=1 when the result of
Positive – Negative is a Negative
Negative – Positive is a Positive [...]
V=0 othewise
So dst and res should not have the same sign and dst and src should also not have the same sign (i.e. src and ret should have the same sign.
From wikipedia:
The overflow flag is thus set when the most significant bit (here considered the sign bit) is changed by adding two numbers with the same sign (or subtracting two numbers with opposite signs). Overflow never occurs when the sign of two addition operands are different (or the sign of two subtraction operands are the same).
From https://sites.google.com/site/arch1utep/home/course_outline/arithmetic_flags:
So dst and res should not have the same sign and dst and src should also not have the same sign (i.e. src and ret should have the same sign.
From wikipedia: