We want to talk to the DDR controller, but directly via one of the four high-speed AXI interfaces, or via the ACP so we have a nice L2 cache in front to help reduce latency?
How to communicate with peripherals (most notably UART1). We need to hook up to one of the GP AXI ports, but this will complicate the Matrix
Bus protocol: See #18 . Bridging will likely be handled in-matrix, right?
Latency: What is our decoding / bridge latency target in # cycles?
Soft logic peripherals: Which ones will we need? Will this increase decoding complexity?
Interrupts: How will the Matrix route interrupts to the Core?
Connections to PS:
Bus protocol: See #18 . Bridging will likely be handled in-matrix, right?
Latency: What is our decoding / bridge latency target in # cycles?
Soft logic peripherals: Which ones will we need? Will this increase decoding complexity?
Interrupts: How will the Matrix route interrupts to the Core?