Open JZJisawesome opened 8 months ago
Pipelined or single-cycle?
I think we can do pipelined: things are split into "stage 1" (the CPU frontend) and "stage 2" (the CPU backend).
However, this is a bit of a misnomer, as these both may contain multiple pipeline stages.
How should we organize the resolution of hazards? Separate hazard resolution unit?
L1 cache? MMU? TLB? How to handle all of this while keeping latency down and not hurting timing (too much)?
CSRs. How do we fit this into the pipeline? Need to flush things in order to properly handle behaviour? What about memory mapped CSRs?
Number # of connections to the Matrix: One for instructions and one for data?
Emulation. Which instructions/CSRs shoudl be emulated? What RISC-V ISA level will we support natively?
Pipelined or single-cycle?
I think we can do pipelined: things are split into "stage 1" (the CPU frontend) and "stage 2" (the CPU backend).
However, this is a bit of a misnomer, as these both may contain multiple pipeline stages.
How should we organize the resolution of hazards? Separate hazard resolution unit?
L1 cache? MMU? TLB? How to handle all of this while keeping latency down and not hurting timing (too much)?
CSRs. How do we fit this into the pipeline? Need to flush things in order to properly handle behaviour? What about memory mapped CSRs?
Number # of connections to the Matrix: One for instructions and one for data?
Emulation. Which instructions/CSRs shoudl be emulated? What RISC-V ISA level will we support natively?