LETC: Reset, Clocking, and Boot

[JZJisawesome]

How to init LETC? Perhaps:

• Conductor initializes LETC's main memory in DRAM. ENSURES FLUSHED FROM ARM L1/L2 cache as appropriate
• Use FCLK signals from the PS to reset LETC, and enable clock when ready. Perhaps also useful to single-step?
• LETC beings executing from DRAM

Questions:

Could we have local SRAM in the PL for LETC to use? Perhaps a boot rom as well?

Use the OCM for lower-latency LETC purposes/bootloader memory?

[JZJisawesome]

Ideas added to top-level block diagram: https://github.com/angry-goose-initiative/wiki/wiki/LETC-Architecture-Overview