JZJisawesome
commented
5 months ago Alrighty I've begun to clean up things on the RTL front!
In addition I've made awesome progress with designer testbenches. If you want to add a new testbench, all you need is the testbench itself (.sv) and a Makefile describing the paths of all RTL files you depend on. The makefiles take care of rest! Furthermore we support simulating with Verilator, Xsim (Vivado) and Vsim (Quartus)!
It would be cool to automate synthesis as well to get timing/area/power estimates as well (though for this project power is not a high priority, and timing takes precedence over area (within reason)).
The individual scripts are terrible. We should switch to Makefiles/etc, and try to improve testbench code reuse.
Also we need to make some changes to account for our switch to a 6 cycle pipeline.