Emulation of instructions for LETC not supported in hardware

[ericjessee]

Steps accomplished so far:

• build rv32ia toochain to facilitate soft divides, etc
• tweak rvsw build so that s-mode applications are built with m-extensions, but m-mode are built without
• decode r-type instructions after control is passed by the exception handler, determine course of action
• implement emulation of rem, div, remu, divu by modifying the stored register contents on the stack
• test functionality by using the / and % operators on signed and unsigned integers in s-mode code (see illegal_instruction_experiments.c)

development currently taking place in this branch!

upcoming todo:

• implement misaligned accesses for instructions, loads, and stores
• ???