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anikau31 / systemc-clang

This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
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Script for running conversion is fixed, convert.py fix is still required #47

Open zhuanhao-wu opened 4 years ago

zhuanhao-wu commented 4 years ago

Description

The script for running the Verilog conversion and the convert.py is fixed and is the tests/verilog-conversion/run-compare.py.

However, convert.py requires changes to correctly convert _hdl.txt into Verilog.

rseac commented 4 years ago

@zhuanhao-wu did you open a PR?

zhuanhao-wu commented 4 years ago

I just made a draft PR #48