TLB (Will_Fire error)

[pragneshp7]

Error: The condition of rule "xyz" depends on the firing of that rule.

`module mkTrans (Trans_Ifc);

Wire#(Req) wr_from_main <- mkWire();
Wire#(Req) wr_to_main <- mkWire();

interface Put from_main;
    method Action put (Req x);
    wr_from_main <= x;
    endmethod
endinterface

interface Get to_main;
    let x = Req {req_type:wr_from_main.req_type , addr:32'h05000000}; 
    method ActionValue#(Req) get;
        $display("%t Its a hit!",$time);
        wr_to_main <= x; 
        return wr_to_main; 
    endmethod
endinterface

endmodule`

[anmolsahoo25]

Dont see the rule

Can you paste the exact error message ?

[anmolsahoo25]

make > log.txt 2>&1

[pragneshp7]

Rectified the error by creating separate rules. New error surfaced which I believe is not related to syntax.

mkdir -p tmp mkdir -p verilog bsc -u -bdir tmp -p +: -simdir tmp -vdir verilog -g driver -verilog driver.bsv checking package dependencies All packages are up to date. verilator -Wall -Wno-STMTDLY -Wno-UNUSED -Wno-BLKSEQ -Wno-PINCONNECTEMPTY -Wno-WIDTH --cc verilog/driver.v --exe sim_main.cpp -I %Error: verilog/driver.v:73: Missing arguments for $display-like format %Error: Exiting due to 1 error(s) %Error: Command Failed /usr/bin/verilator_bin -Wall -Wno-STMTDLY -Wno-UNUSED -Wno-BLKSEQ -Wno-PINCONNECTEMPTY -Wno-WIDTH --cc verilog/driver.v --exe sim_main.cpp -I make: *** [Makefile:14: all] Error 10

[pragneshp7]

Rectified. Argument missing in $display.