FEAT: change symbol pin locations

[HaiwenZhang]

Hi pyaedt Teams,

I want to use change Sparameter pin locations in Designer, but I can't find any API in pyaedt. So I implement change pin locations API in pyaedt according to IronPython oSymbolManager.EditSymbolAndUpdateComps API. But I met a problem in the implementation.

The Pin location of the S parameter I imported through pyaedt's create_touchstone_component is shown in the figure below.

After calling my change_symbol_pin_locations API, the pin locations of the S parameters are as shown below.

From the circuit diagram of Designer, changing the pin locations of S parameters is successful. However, when I add port1 to the pin name "DDR_DM_DBI0_BGA_BE47" and port2 to the pin name "DDR_CH3_DM_DBI0_DIE_7976", and do Linear Network Analysis. It seems that there is something wrong with the expression of S parameters

The graph of S(port1, port2) should show the characteristics of insertion loss, but the simulation results show that it does not.

Therefore, I would like to ask you guys to help see where I am going wrong in my implementation.

Here is my demo code, the compressed file is the S parameter file.

import os
from pyaedt import Circuit
current_path = os.path.split(os.path.realpath(__file__))[0]
cir = Circuit("test")
cir.modeler.schematic_units = "mil"
ts_path = os.path.join(current_path, "connector_model.s4p")
ts_component = cir.modeler.schematic.create_touchstone_component(ts_path, show_bitmap=False)
pin_locations = {
   "left": [
       'DDR_CH3_DM_DBI0_BGA_BE47',
       'DDR_CH3_DM_DBI1_BGA_BJ50',
       'DDR_CH3_DM_DBI1_DIE_12471'  
   ],
   "right": [
       'DDR_CH3_DM_DBI0_DIE_7976'
   ]
}
ts_component.change_symbol_pin_locations(pin_locations)
cir.save_project()

connector_model.zip

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[maxcapodi78]

@HaiwenZhang It seems that the problem is in AEDT API Command. It expects the Terminal Arguments in the correct order. Try the following: comment the Terminal args assignments in left_pins and right_pins for loop and add this right after. It worked for me.

        for pin_name in self.model_data.props.get("PortNames",[]):
            terminals_arg.append("TermAttributes:=")
            terminals_arg.append([pin_name, pin_name, 0 if pin_name in left_pin else 1, 0, -1, ""])

[HaiwenZhang]

@maxcapodi78 Thank you very much. I will experiment on my side and do enough case tests. I will optimize my code implementation and commit my code.

[HaiwenZhang]

@maxcapodi78 I don't know why my PR fails in the automated tests in Github CI CD. Maybe you need to git cherry-pick.

[Samuelopez-ansys]

Cherry picked : https://github.com/ansys/pyaedt/pull/4956