VHDL name parsing issue

[Nolica]

Hi,

VHDL grammar is not correct to parse a bus name with attribute part:

ck_event <= CK'event;  -- OK
ck_event <= CK(0)'event -- KO

I think it's due to the following modification in the original grammar :

// was
//   name
//     : simple_name
//     | operator_symbol
//     | selected_name
//     | indexed_name
//     | slice_name
//     | attribute_name
//     ;
// changed to avoid left-recursion to name (from selected_name, indexed_name,
// slice_name, and attribute_name, respectively)
// (2.2.2004, e.f.)
name
  : selected_name  
  | name_part ( DOT name_part)*
  ;

Anyone to help me to correct the actual grammar file?

BR Olivier

[Nolica]

I propose the following grammar correction. it's working on my side but it requests to update your custom listener/visitor to work.

name
  : ( identifier | operator_symbol ) name_part
  ;

operator_symbol
  : STRING_LITERAL
  ;

name_part
  : ( ( function_call_part )? ( selected_name_part | indexed_name_part | slice_name_part | attribute_name_part ) name_part )?
  ;

selected_name
   : identifier ( DOT suffix )*
   ;

selected_name_part
  : ( DOT suffix )+
  ;

indexed_name_part
  : LPAREN expression ( COMMA expression )* RPAREN
  ;

slice_name_part
  : LPAREN discrete_range RPAREN
  ;

attribute_name_part
  : ( signature )? APOSTROPHE attribute_designator ( LPAREN expression RPAREN )?
  ;

function_call_part
  : LPAREN actual_parameter_part RPAREN
  ;

[Nolica]

Simplified grammar correction :

name
  : ( identifier | STRING_LITERAL ) ( name_part )*
  ;

name_part
  : selected_name_part
  | function_call_or_indexed_name_part
  | slice_name_part
  | attribute_name_part
  ;

selected_name
   : identifier ( DOT suffix )*
   ;

selected_name_part
  : ( DOT suffix )+
  ;

function_call_or_indexed_name_part
  : LPAREN actual_parameter_part RPAREN
  ;

slice_name_part
  : LPAREN discrete_range RPAREN
  ;

attribute_name_part
  : ( signature )? APOSTROPHE attribute_designator ( LPAREN expression RPAREN )?
  ;

[KvanTTT]

• Please use three back-ticks syntax for code blocks in future.
• You are welcome to make a PR with your corrections.

[Nolica]

Hello KvanTTT,

Sorry for the three back-ticks About this issue, I have identified the root cause : it's due to a previous modification

0247bb29f5341dc1021dd827614fdca312f30630
File  committed on 13 Jan 2015:
Modified function call, selected name and slice grammar rules.

New version of grammar successfully analyzed standard libraries (STD and
IEEE). Sources of that files added to example folder.

VHDL is a very complex language and validate the grammar only with the standard libraries is not adequate. I am reassured to see that the correction I propose above looks like the version before this commit on 13 Jan 2015

I will continue to validate the grammar on my side and propose a full update asap : it's a validation on about more than 800 vhdl files

Best regards