Unable to build the project

[apexintern1]

The link to the repository, alkali-csd-hw. I have been trying to build the project, while I issued the "make all" command, during "make vivado" command the building has been failing, has it cannot the design due to the following errors, ( I got when I ran "source vivado_block_design.tcl" vivado (version 2019.2)

INFO: [BD_TCL-6] Checking if the following IPs exist in the project's IP catalog:
xilinx.com:ip:axi_gpio:2.0 xilinx.com:ip:axi_protocol_converter:2.1 xilinx.com:ip:axi_uartlite:2.0 xilinx.com:ip:ila:6.2 xilinx.com:ip:proc_sys_reset:5.0 xilinx.com:ip:system_management_wiz:1.3 xilinx.com:ip:xlconcat:2.1 xilinx.com:ip:zynq_ultra_ps_e:3.3 xilinx.com:hls:compute:1.0 xilinx.com:hls:fetch:1.0 xilinx.com:ip:fifo_generator:13.2 xilinx.com:ip:blk_mem_gen:8.4 xilinx.com:hls:load:1.0 xilinx.com:ip:smartconnect:1.0 xilinx.com:hls:store:1.0 . WARNING: [Coretcl 2-175] No Catalog IPs found WARNING: [Coretcl 2-175] No Catalog IPs found WARNING: [Coretcl 2-175] No Catalog IPs found WARNING: [Coretcl 2-175] No Catalog IPs found ERROR: [BD_TCL-115] The following IPs are not found in the IP Catalog: xilinx.com:hls:compute:1.0 xilinx.com:hls:fetch:1.0 xilinx.com:hls:load:1.0 xilinx.com:hls:store:1.0

Resolution: Please add the repository containing the IP(s) to the project. WARNING: [BD_TCL-1003] Will not continue with creation of design due to the error(s) above.

To resolve the issue, I tried to add the missing IPs from the IP catalogue in the vivado. But, unfortunately I was not able to find any of the missing IPs in the catalogue.

System - Ubuntu 18.04.6 LTS Kernel version - 4.15.0-204-generic

Please help me find a way to resolve the issues and successfully build the project. Thanks in advance

[kgugala]

HI @apexintern1, I just rebuilt the whole project from scratch and it went fine. Do you use provided Docker flow, or do you build the whole project natively?

Are you able to capture the whole build flow and share here?

[apexintern1]

I used the provided Docker flow. I just ran the command "make all" as mentioned in the repository.

[kgugala]

Can you run clean build and share the whole log? Could your Vivado installation be somehow incomplete? Or maybe scattered across a few directories (and linked with symlinks), so Docker container in which the whole build happen does not have access to all the files?

[apexintern1]

So, I ran "make clean" and "make all" commands as you said, here is the log (not total log) log_file.log

alkali-csd-hw/build/an300/project_vta/project_vta.runs/pcie4_uscale_plus_0_synth_1/rumne.log file, *** Running vivado with args -log pcie4_uscale_plus_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source pcie4_uscale_plus_0.tcl

** Vivado v2019.2 (64-bit) SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source pcie4_uscale_plus_0.tcl -notrace INFO: [Common 17-41] Interrupt caught. Command should exit soon. INFO: [Common 17-41] Interrupt caught. Command should exit soon. INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-2338] Canceling the changes to the IP catalog. Reverting the catalog back to its previous state. INFO: [IP_Flow 19-2340] The IP catalog has been returned to its previous state. update_ip_catalog: Time (s): cpu = 00:00:03 ; elapsed = 00:00:10 . Memory (MB): peak = 1477.539 ; gain = 8.004 ; free physical = 2481 ; free virtual = 8392 INFO: [Common 17-344] 'update_ip_catalog' was cancelled INFO: [Common 17-344] 'source' was cancelled INFO: [Common 17-206] Exiting Vivado at Mon Mar 6 15:18:24 2023...

[kgugala]

can you share /home/apexplus/alkali-csd-hw/build/an300/project_vta/project_vta.runs/synth_1/runme.log? This one should have the real error message

[apexintern1]

But, the folder did not contain the runme.log file.

[kgugala]

the log you shared says:

Run output will be captured here: /home/apexplus/alkali-csd-hw/build/an300/project_vta/project_vta.runs/synth_1/runme.log

Unfortunately, contents of this file are not displayed in the output, so we need to get it to see what really failed.

Actually, when I look at the log I see that you cancelled the run with ctrl-C, is that right? Before this the whole log looks fine, please let it run till the end.

[apexintern1]

As per log, the file should be present which isn't, and I cancelled the run with ctrl-C, because after the log shows "Waiting for synth_1 to finish..." after 30-120 secs the screen gets frozen and I need restart the system, this has happened for 5 times now.

[kgugala]

after Launched synth_1... Vivado synthesizes the design. It takes some time to finish depending on the machine it could be even 20 minutes (depending on the machine).

If your whole machine freezes, I'd assume you're running out of memory. Can you run e.g. htop in a separate terminal and monitor the resources?

[apexintern1]

Yes, almost 90% of memory is used and CPU engine reach nearly 100%. So, what to do now?

[kgugala]

We cannot do much about Vivado's memory demands. I'd suggest closing all the background processes (and freeing some memory), enabling swap (but this could end up in very long build time), or simply use a computer with more memory

[apexintern1]

I have increased the system's memory and ran the "make all" command, But I got new errors. This is the log file after "launching synth_1". logfile1.log

[kgugala]

did you start from scratch? or ran make all on previously failed build?

[apexintern1]

Yes, I started from scratch.

[kgugala]

hmm, can you share the whole log - including code generation before Vivado launch. I just ran the whole flow from a clean clone and it finished w/o issues

[apexintern1]

Can you tell me the hardware specifications of your system and FPGA card? logfile2.log

[apexintern1]

Can you tell me the hardware specifications of your system and FPGA card? logfile2.log