Closed michalsieron closed 1 year ago
This PR moves part of version.py body to separate function read_ident in utils.py so it can be used in other places as well.
version.py
read_ident
utils.py
In particular, I added read_ident call after each wb.open() in current scripts, so it is easier to share used configuration when copying console log.
wb.open()
``` $ TARGET=ddr4_datacenter_test_board python rowhammer_tester/scripts/bios_console.py Using generated target files in: build/ddr4_datacenter_test_board Board info: Row Hammer Tester SoC on xc7k160tffg676-1, git: ae0efa3e328830c277e2f712c700bfbb48b0812f 2022-11-23 14:28:01 LiteX Crossover UART created: /dev/pts/6 Using serial backend: auto picocom v3.1 port is : /dev/pts/6 flowcontrol : none baudrate is : 1000000 parity is : none databits are : 8 stopbits are : 1 escape is : C-a local echo is : no noinit is : no noreset is : no hangup is : no nolock is : no send_cmd is : sz -vv receive_cmd is : rz -vv -E imap is : omap is : emap is : crcrlf,delbs, logfile is : none initstring : none exit_after is : not set exit is : no Type [C-a] [C-h] to see available commands Terminal ready __ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/|_| Build your hardware, easily! (c) Copyright 2012-2022 Enjoy-Digital (c) Copyright 2007-2015 M-Labs BIOS built on Nov 23 2022 14:28:04 BIOS CRC passed (c5d12b2a) LiteX git sha1: a63ec872b --=============== SoC ==================-- CPU: VexRiscv_Min @ 100MHz BUS: WISHBONE 32-bit @ 4GiB CSR: 32-bit data ROM: 64KiB SRAM: 8KiB L2: 0KiB SDRAM: 1048576KiB 64-bit @ 800MT/s (CL-9 CWL-9) --========== Initialization ============-- Initializing SDRAM @0x40000000... Switching SDRAM to software control. Write latency calibration: m0:6 m1:6 m2:6 m3:6 m4:6 m5:6 m6:6 m7:6 m8:6 m9:6 m10:6 m11:6 m12:6 m13:6 m14:6 m15:6 Read leveling: m0, b00: |00000000000000000000000000000000| delays: - m0, b01: |00000000000000000000000000000000| delays: - m0, b02: |00000000000000000000000000000000| delays: - m0, b03: |11111111000000000000000000000000| delays: 03+-03 m0, b04: |00000000001111111111111100000000| delays: 17+-07 m0, b05: |00000000000000000000000000011111| delays: 29+-02 m0, b06: |00000000000000000000000000000000| delays: - m0, b07: |00000000000000000000000000000000| delays: - best: m0, b04 delays: 17+-07 m1, b00: |00000000000000000000000000000000| delays: - m1, b01: |00000000000000000000000000000000| delays: - m1, b02: |00000000000000000000000000000000| delays: - m1, b03: |11111111000000000000000000000000| delays: 04+-04 m1, b04: |00000000001111111111111110000000| delays: 17+-07 m1, b05: |00000000000000000000000000001111| delays: 30+-02 m1, b06: |00000000000000000000000000000000| delays: - m1, b07: |00000000000000000000000000000000| delays: - best: m1, b04 delays: 17+-07 ... ```
This PR moves part of
version.pybody to separate functionread_identinutils.pyso it can be used in other places as well.In particular, I added
read_identcall after eachwb.open()in current scripts, so it is easier to share used configuration when copying console log.Example log. Notice board info in the second line of the output
``` $ TARGET=ddr4_datacenter_test_board python rowhammer_tester/scripts/bios_console.py Using generated target files in: build/ddr4_datacenter_test_board Board info: Row Hammer Tester SoC on xc7k160tffg676-1, git: ae0efa3e328830c277e2f712c700bfbb48b0812f 2022-11-23 14:28:01 LiteX Crossover UART created: /dev/pts/6 Using serial backend: auto picocom v3.1 port is : /dev/pts/6 flowcontrol : none baudrate is : 1000000 parity is : none databits are : 8 stopbits are : 1 escape is : C-a local echo is : no noinit is : no noreset is : no hangup is : no nolock is : no send_cmd is : sz -vv receive_cmd is : rz -vv -E imap is : omap is : emap is : crcrlf,delbs, logfile is : none initstring : none exit_after is : not set exit is : no Type [C-a] [C-h] to see available commands Terminal ready __ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/|_| Build your hardware, easily! (c) Copyright 2012-2022 Enjoy-Digital (c) Copyright 2007-2015 M-Labs BIOS built on Nov 23 2022 14:28:04 BIOS CRC passed (c5d12b2a) LiteX git sha1: a63ec872b --=============== SoC ==================-- CPU: VexRiscv_Min @ 100MHz BUS: WISHBONE 32-bit @ 4GiB CSR: 32-bit data ROM: 64KiB SRAM: 8KiB L2: 0KiB SDRAM: 1048576KiB 64-bit @ 800MT/s (CL-9 CWL-9) --========== Initialization ============-- Initializing SDRAM @0x40000000... Switching SDRAM to software control. Write latency calibration: m0:6 m1:6 m2:6 m3:6 m4:6 m5:6 m6:6 m7:6 m8:6 m9:6 m10:6 m11:6 m12:6 m13:6 m14:6 m15:6 Read leveling: m0, b00: |00000000000000000000000000000000| delays: - m0, b01: |00000000000000000000000000000000| delays: - m0, b02: |00000000000000000000000000000000| delays: - m0, b03: |11111111000000000000000000000000| delays: 03+-03 m0, b04: |00000000001111111111111100000000| delays: 17+-07 m0, b05: |00000000000000000000000000011111| delays: 29+-02 m0, b06: |00000000000000000000000000000000| delays: - m0, b07: |00000000000000000000000000000000| delays: - best: m0, b04 delays: 17+-07 m1, b00: |00000000000000000000000000000000| delays: - m1, b01: |00000000000000000000000000000000| delays: - m1, b02: |00000000000000000000000000000000| delays: - m1, b03: |11111111000000000000000000000000| delays: 04+-04 m1, b04: |00000000001111111111111110000000| delays: 17+-07 m1, b05: |00000000000000000000000000001111| delays: 30+-02 m1, b06: |00000000000000000000000000000000| delays: - m1, b07: |00000000000000000000000000000000| delays: - best: m1, b04 delays: 17+-07 ... ```