This PR adds an ability to perform memtest of RAM bypassing limitation of 32-bit address system bus.
It achieves this by usage of existing BIST modules from LiteX.
It also includes rebase of litex and litedram submodules on top of the current upstream master branches.
I added documentation for sdram_hw_test and updates in LiteX and litedram commits include ability to read memory size from the SPD, so it should be ready to merge
This PR adds an ability to perform memtest of RAM bypassing limitation of 32-bit address system bus. It achieves this by usage of existing BIST modules from LiteX.
It also includes rebase of litex and litedram submodules on top of the current upstream master branches.