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antmicro / rowhammer-tester

https://antmicro.github.io/rowhammer-tester/
Apache License 2.0
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Build fails when attempting to expand payload to 1MB #34

Closed sqazi closed 3 years ago

sqazi commented 3 years ago

This is what happens at the end:

ERROR: [DRC UTLZ-1] Resource utilization: F7 Muxes over-utilized in Top Level Design (This design requires more F7 Muxes cells than are available in the target device. This design requires 273875 of such cell types but only 115200 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.) ERROR: [DRC UTLZ-1] Resource utilization: F8 Muxes over-utilized in Top Level Design (This design requires more F8 Muxes cells than are available in the target device. This design requires 136545 of such cell types but only 57600 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.) ERROR: [DRC UTLZ-1] Resource utilization: LUT as Distributed RAM over-utilized in Top Level Design (This design requires more LUT as Distributed RAM cells than are available in the target device. This design requires 525960 of such cell types but only 101760 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter "drc.disableLUTOverUtilError" to 1 to change this error to warning.) ERROR: [DRC UTLZ-1] Resource utilization: LUT as Memory over-utilized in Top Level Design (This design requires more LUT as Memory cells than are available in the target device. This design requires 525968 of such cell types but only 101760 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter "drc.disableLUTOverUtilError" to 1 to change this error to warning.) ERROR: [DRC UTLZ-1] Resource utilization: MUXF7 over-utilized in Top Level Design (This design requires more MUXF7 cells than are available in the target device. This design requires 273875 of such cell types but only 115200 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.) ERROR: [DRC UTLZ-1] Resource utilization: MUXF8 over-utilized in Top Level Design (This design requires more MUXF8 cells than are available in the target device. This design requires 136545 of such cell types but only 57600 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.) ERROR: [DRC UTLZ-1] Resource utilization: RAMD64E over-utilized in Top Level Design (This design requires more RAMD64E cells than are available in the target device. This design requires 524288 of such cell types but only 101760 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.) ERROR: [DRC UTLZ-1] Resource utilization: Slice LUTs over-utilized in Top Level Design (This design requires more Slice LUTs cells than are available in the target device. This design requires 660461 of such cell types but only 230400 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter "drc.disableLUTOverUtilError" to 1 to change this error to warning.) INFO: [Vivado_Tcl 4-198] DRC finished with 8 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. ERROR: [Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run. INFO: [Common 17-83] Releasing license: Implementation 8 Infos, 0 Warnings, 0 Critical Warnings and 9 Errors encountered. place_design failed place_design: Time (s): cpu = 00:03:53 ; elapsed = 00:02:21 . Memory (MB): peak = 14902.289 ; gain = 0.000 ; free physical = 8299 ; free virtual = 21718 ERROR: [Common 17-39] 'place_design' failed due to earlier errors.

while executing

"place_design -directive default" (file "zcu104.tcl" line 45) INFO: [Common 17-206] Exiting Vivado at Sat Jan 16 10:44:45 2021... Traceback (most recent call last): File "rowhammer_tester/targets/zcu104.py", line 244, in main() File "rowhammer_tester/targets/zcu104.py", line 241, in main common.run(args, builder, build_kwargs, target_name=target_name) File "/home/sqazi/fpga/litex-rowhammer-tester/rowhammer_tester/targets/common.py", line 431, in run builder.build(build_kwargs, run=args.build) File "/home/sqazi/fpga/litex-rowhammer-tester/third_party/litex/litex/soc/integration/builder.py", line 214, in build vns = self.soc.build(build_dir=self.gateware_dir, kwargs) File "/home/sqazi/fpga/litex-rowhammer-tester/third_party/litex/litex/soc/integration/soc.py", line 1048, in build return self.platform.build(self, *args, kwargs) File "/home/sqazi/fpga/litex-rowhammer-tester/third_party/litex/litex/build/xilinx/platform.py", line 53, in build return self.toolchain.build(self, *args, *kwargs) File "/home/sqazi/fpga/litex-rowhammer-tester/third_party/litex/litex/build/xilinx/vivado.py", line 344, in build _run_script(script) File "/home/sqazi/fpga/litex-rowhammer-tester/third_party/litex/litex/build/xilinx/vivado.py", line 93, in _run_script raise OSError("Subprocess failed") OSError: Subprocess failed make[1]: [Makefile:31: build] Error 1 make[1]: Leaving directory '/home/sqazi/fpga/litex-rowhammer-tester'

Can we figure out why it happens and if the situation can be improved? An alternative proposal (if this is not possible to improve) is to introduce the concept of small bounded number of nested loops to reduce the payload size.

jedrzejboczar commented 3 years ago

Payload Executor was not fully utilizingthe BRAMs on the FPGA. I just added changes that fix this issue. I was able to build the bitstream with 1MB of payload memory:

python rowhammer_tester/targets/zcu104.py --payload-size 0x100000 --build

With this setting it is currently using 88.14% ob Block RAMs on the ZCU104.

In the current version reading payload memory has a latency of 1, so it is simple to prefetch the instruction and there is no difference in the behavior of the Payload Executor. Vivado will warn about "sub-optimal timings" as we don't buffer the output from BRAM. We could fix that, potentially improving build times (building with 1MB payload took ~17.5 minutes on my machine), but that would increase memory latency to 2 cycles and would complicate the logic of the executor. It would also require increasing the time taken by a loop jump and probably we would increase minimal timeslice to 2 depending on how we would implement pipelining. If that's not necessary we may stick with the current version.