v1.2.0 errata

[osterwood]

Rework required for I2C-based gateware loading:

• Connect J6 CRESET_B to U5 pin 10 (GPIO2)
• Connect J6 USER_SDA to SDA_CL (left side of R41)
• Connect J6 USER_SCL to SCL_CL (left side of R42)

Without these changes, a programmer must be connected to J6 (the CL_PROG) header to load gateware onto the Crosslink FPGA.

Design change suggestions for the next revision:

• Add net connection between CRESET_B and U5 pin 10.
• Combine USER_SDA and SDA_CL nets
• Combine USER_SCL and SCL_CL nets

[osterwood]

v1.2.0 hardware shipped by Capable Robot has the rework noted above

[pkatarzynski]

The changes listed above are included in revision 1.3.0.