Request for Inclusion of Latest Verilator `master` Branch in Repository

[opensource-elearning]

I acknowledge the invaluable contributions of Wilson Snyder and Antmicro to Verilator, enabling the utilization of fundamental SystemVerilog and UVM testbenches.

To enhance the benefits of this repository, we propose incorporating the master Verilator branch. This integration would provide access to the latest bug fixes, optimizations, and feature enhancements, including those related to SystemVerilog/UVM.

As a new user, I understand the importance of having access to the most recent Verilator version. However, we lack the C/C++ expertise to independently maintain a master branch.

I kindly request the establishment of a process to periodically update this repository with the latest Verilator master branch. This would ensure that users have access to the most advanced features and improvements, while also benefiting from bug fixes and performance enhancements.

[opensource-elearning]

@kbieganski @mgielda @kgugala @kiryk @RRozak @tgorochowik

[pgielda]

I am confused here, Verilator is referenced in this repository - as a submodule: https://github.com/antmicro/verilator-verification-features-tests/tree/main/verilator In fact two times (the "vanilla" version and the fork with crave).

Also - there is no real code here, its a set of tests and pointers to right commits to be able to reproduce those tests. We're upstreaming all the changes directly to https://github.com/verilator/verilator so just use the official repo.

[opensource-elearning]

When we run UVM simulation on Verilator master branch it got stuck on uvm run test.

Even in this same repo we have updated submodule with Verilator master branch but still we face the same issue that is being mentioned in the one of the Verilator issues also

https://github.com/verilator/verilator/issues/1538#issuecomment-1774943042

may be @kbieganski or @tgorochowik knows why it is working here with only specific commit only and not in Master branch of Verilator.

I don't know what changes this repo contains, but the commit in this repo works for Verilator and UVM.

[pgielda]

UVM support is far from complete, so I am sure there are issues. Having said that I will ask around on why this does not work with current master. The one referenced here is a commit from the main branch, just ~3 months old. It might be a regression. Also bear in mind that the uvm library currently referenced here is: https://github.com/antmicro/uvm-verilator/tree/2e667ac506c12e91d81bde62fe2c08d992731bd4 and not a vanilla version of it.

[opensource-elearning]

I concur with your assessment that comprehensive UVM support, including the Register Abstraction Layer (RAL) model, is not yet fully implemented.

I am currently utilizing UVM from a specific branch that is part of a submodule. The commit you referenced has been applied to this branch.

I have successfully executed the mem-tb test case, indicating that UVM and Verilator are properly configured.

However, we are unable to leverage the latest Verilator bug fixes, optimizations, and enhancements.

Despite this limitation, we are appreciative of the contributions of the open-source community.

Thank you for your prompt response @pgielda

[tgorochowik]

We have a dependabot job set up which periodically tries to update Verilator here.

Currently the update job fails, because it exceeds the 6h GitHub actions limit. That's why it wasn't updated in 3 months. It's possible that newer verilator takes more time to execute, that more tests actually run which makes it longer or maybe some tests just get stuck.

This needs to be investigated before we can update Verilator here

[opensource-elearning]

@tgorochowik, Could someone from your team please consider addressing this issue when they have availability?

We would greatly appreciate any assistance in resolving this matter.

[pgielda]

It will definitely be addressed at some point. Meanwhile I am closing this issue.

[tgorochowik]

@opensource-elearning Verilator has been updated this morning to a recent revision (latest commit as of this morning)

[opensource-elearning]

Thanks @tgorochowik for Update.

I have just checked with with latest updated version on this repo.

Now I am not able to run UVM mem-tb example testbench present at tests/uvm-testbenches/mem-tb

It is getting stuck at Running test as shown below

mem_tb-sim/mem_tb +UVM_TESTNAME=mem_wr_rd_test
UVM_INFO /tools/uvm/ieee_uvm_1800.2_2017/src/base/uvm_root.svh(449) @ 0: reporter [UVM/RELNOTES]
  ***********       IMPORTANT RELEASE NOTES         ************

  This implementation of the UVM Library deviates from the 1800.2-2017
  standard.  See the DEVIATIONS.md file contained in the release
  for more details.

----------------------------------------------------------------
Accellera:1800.2-2017:UVM:1.0

All copyright owners for this kit are listed in NOTICE.txt
All Rights Reserved Worldwide
----------------------------------------------------------------

      (Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO /tools/uvm/ieee_uvm_1800.2_2017/src/base/uvm_root.svh(517) @ 0: reporter [NO_DPI_TSTNAME] UVM_NO_DPI defined--getting UVM_TESTNAME directly, without DPI
UVM_INFO @ 0: reporter [RNTST] Running test mem_wr_rd_test...

Previously it is working fine with feae9ca commit for Verilator with version 5.019

mem_tb-sim/mem_tb +UVM_TESTNAME=mem_wr_rd_test
UVM_INFO /tools/uvm/ieee_uvm_1800.2_2017/src/base/uvm_root.svh(449) @ 0: reporter [UVM/RELNOTES]
  ***********       IMPORTANT RELEASE NOTES         ************

  This implementation of the UVM Library deviates from the 1800.2-2017
  standard.  See the DEVIATIONS.md file contained in the release
  for more details.

----------------------------------------------------------------
Accellera:1800.2-2017:UVM:1.0

All copyright owners for this kit are listed in NOTICE.txt
All Rights Reserved Worldwide
----------------------------------------------------------------

      (Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO /tools/uvm/ieee_uvm_1800.2_2017/src/base/uvm_root.svh(517) @ 0: reporter [NO_DPI_TSTNAME] UVM_NO_DPI defined--getting UVM_TESTNAME directly, without DPI
UVM_INFO @ 0: reporter [RNTST] Running test mem_wr_rd_test...
UVM_INFO /tools/uvm/ieee_uvm_1800.2_2017/src/base/uvm_traversal.svh(289) @ 0: reporter [UVM/COMP/NAMECHECK] This implementation of the component name checks requires DPI to be enabled
UVM_WARNING /tools/uvm/ieee_uvm_1800.2_2017/src/base/uvm_traversal.svh(274) @ 0: reporter [UVM/COMP/NAME] the name "uvm_test_top" of the component "uvm_test_top" violates the uvm component name constraints
UVM_WARNING /tools/uvm/ieee_uvm_1800.2_2017/src/base/uvm_traversal.svh(274) @ 0: reporter [UVM/COMP/NAME] the name "env" of the component "uvm_test_top.env" violates the uvm component name constraints
UVM_WARNING /tools/uvm/ieee_uvm_1800.2_2017/src/base/uvm_traversal.svh(274) @ 0: reporter [UVM/COMP/NAME] the name "mem_agnt" of the component "uvm_test_top.env.mem_agnt" violates the uvm component name constraints
UVM_WARNING /tools/uvm/ieee_uvm_1800.2_2017/src/base/uvm_traversal.svh(274) @ 0: reporter [UVM/COMP/NAME] the name "driver" of the component "uvm_test_top.env.mem_agnt.driver" violates the uvm component name constraints
UVM_WARNING /tools/uvm/ieee_uvm_1800.2_2017/src/base/uvm_traversal.svh(274) @ 0: reporter [UVM/COMP/NAME] the name "rsp_port" of the component "uvm_test_top.env.mem_agnt.driver.rsp_port" violates the uvm component name constraints
UVM_WARNING /tools/uvm/ieee_uvm_1800.2_2017/src/base/uvm_traversal.svh(274) @ 0: reporter [UVM/COMP/NAME] the name "seq_item_port" of the component "uvm_test_top.env.mem_agnt.driver.seq_item_port" violates the uvm component name constraints
UVM_WARNING /tools/uvm/ieee_uvm_1800.2_2017/src/base/uvm_traversal.svh(274) @ 0: reporter [UVM/COMP/NAME] the name "monitor" of the component "uvm_test_top.env.mem_agnt.monitor" violates the uvm component name constraints
UVM_WARNING /tools/uvm/ieee_uvm_1800.2_2017/src/base/uvm_traversal.svh(274) @ 0: reporter [UVM/COMP/NAME] the name "item_collected_port" of the component "uvm_test_top.env.mem_agnt.monitor.item_collected_port" violates the uvm component name constraints
UVM_WARNING /tools/uvm/ieee_uvm_1800.2_2017/src/base/uvm_traversal.svh(274) @ 0: reporter [UVM/COMP/NAME] the name "sequencer" of the component "uvm_test_top.env.mem_agnt.sequencer" violates the uvm component name constraints
UVM_WARNING /tools/uvm/ieee_uvm_1800.2_2017/src/base/uvm_traversal.svh(274) @ 0: reporter [UVM/COMP/NAME] the name "req_fifo" of the component "uvm_test_top.env.mem_agnt.sequencer.req_fifo" violates the uvm component name constraints
UVM_WARNING /tools/uvm/ieee_uvm_1800.2_2017/src/base/uvm_traversal.svh(274) @ 0: reporter [UVM/COMP/NAME] the name "get_ap" of the component "uvm_test_top.env.mem_agnt.sequencer.req_fifo.get_ap" violates the uvm component name constraints
UVM_WARNING /tools/uvm/ieee_uvm_1800.2_2017/src/base/uvm_traversal.svh(274) @ 0: reporter [UVM/COMP/NAME] the name "get_peek_export" of the component "uvm_test_top.env.mem_agnt.sequencer.req_fifo.get_peek_export" violates the uvm component name constraints
UVM_WARNING /tools/uvm/ieee_uvm_1800.2_2017/src/base/uvm_traversal.svh(274) @ 0: reporter [UVM/COMP/NAME] the name "put_ap" of the component "uvm_test_top.env.mem_agnt.sequencer.req_fifo.put_ap" violates the uvm component name constraints
UVM_WARNING /tools/uvm/ieee_uvm_1800.2_2017/src/base/uvm_traversal.svh(274) @ 0: reporter [UVM/COMP/NAME] the name "put_export" of the component "uvm_test_top.env.mem_agnt.sequencer.req_fifo.put_export" violates the uvm component name constraints
UVM_WARNING /tools/uvm/ieee_uvm_1800.2_2017/src/base/uvm_traversal.svh(274) @ 0: reporter [UVM/COMP/NAME] the name "rsp_export" of the component "uvm_test_top.env.mem_agnt.sequencer.rsp_export" violates the uvm component name constraints
UVM_WARNING /tools/uvm/ieee_uvm_1800.2_2017/src/base/uvm_traversal.svh(274) @ 0: reporter [UVM/COMP/NAME] the name "seq_item_export" of the component "uvm_test_top.env.mem_agnt.sequencer.seq_item_export" violates the uvm component name constraints
UVM_WARNING /tools/uvm/ieee_uvm_1800.2_2017/src/base/uvm_traversal.svh(274) @ 0: reporter [UVM/COMP/NAME] the name "sqr_rsp_analysis_fifo" of the component "uvm_test_top.env.mem_agnt.sequencer.sqr_rsp_analysis_fifo" violates the uvm component name constraints
UVM_WARNING /tools/uvm/ieee_uvm_1800.2_2017/src/base/uvm_traversal.svh(274) @ 0: reporter [UVM/COMP/NAME] the name "analysis_export" of the component "uvm_test_top.env.mem_agnt.sequencer.sqr_rsp_analysis_fifo.analysis_export" violates the uvm component name constraints
UVM_WARNING /tools/uvm/ieee_uvm_1800.2_2017/src/base/uvm_traversal.svh(274) @ 0: reporter [UVM/COMP/NAME] the name "get_ap" of the component "uvm_test_top.env.mem_agnt.sequencer.sqr_rsp_analysis_fifo.get_ap" violates the uvm component name constraints
UVM_WARNING /tools/uvm/ieee_uvm_1800.2_2017/src/base/uvm_traversal.svh(274) @ 0: reporter [UVM/COMP/NAME] the name "get_peek_export" of the component "uvm_test_top.env.mem_agnt.sequencer.sqr_rsp_analysis_fifo.get_peek_export" violates the uvm component name constraints
UVM_WARNING /tools/uvm/ieee_uvm_1800.2_2017/src/base/uvm_traversal.svh(274) @ 0: reporter [UVM/COMP/NAME] the name "put_ap" of the component "uvm_test_top.env.mem_agnt.sequencer.sqr_rsp_analysis_fifo.put_ap" violates the uvm component name constraints
UVM_WARNING /tools/uvm/ieee_uvm_1800.2_2017/src/base/uvm_traversal.svh(274) @ 0: reporter [UVM/COMP/NAME] the name "put_export" of the component "uvm_test_top.env.mem_agnt.sequencer.sqr_rsp_analysis_fifo.put_export" violates the uvm component name constraints
UVM_WARNING /tools/uvm/ieee_uvm_1800.2_2017/src/base/uvm_traversal.svh(274) @ 0: reporter [UVM/COMP/NAME] the name "mem_scb" of the component "uvm_test_top.env.mem_scb" violates the uvm component name constraints
UVM_WARNING /tools/uvm/ieee_uvm_1800.2_2017/src/base/uvm_traversal.svh(274) @ 0: reporter [UVM/COMP/NAME] the name "item_collected_export" of the component "uvm_test_top.env.mem_scb.item_collected_export" violates the uvm component name constraints
---------------------------------------
Name          Type          Size  Value
---------------------------------------
mem_seq_item  mem_seq_item  -     @212
  addr        integral      2     'h2
  wr_en       integral      1     'h1
  rd_en       integral      1     'h0
  wdata       integral      8     'h76
---------------------------------------
UVM_INFO hdl/mem_scoreboard.sv(59) @ 25000: uvm_test_top.env.mem_scb [mem_scoreboard] ------ :: WRITE DATA       :: ------
UVM_INFO hdl/mem_scoreboard.sv(60) @ 25000: uvm_test_top.env.mem_scb [mem_scoreboard] Addr: 2
UVM_INFO hdl/mem_scoreboard.sv(61) @ 25000: uvm_test_top.env.mem_scb [mem_scoreboard] Data: 76
UVM_INFO hdl/mem_scoreboard.sv(62) @ 25000: uvm_test_top.env.mem_scb [mem_scoreboard] ------------------------------------
UVM_INFO hdl/mem_base_test.sv(54) @ 25000: uvm_test_top [mem_wr_rd_test] ---------------------------------------
UVM_INFO hdl/mem_base_test.sv(55) @ 25000: uvm_test_top [mem_wr_rd_test] ----           TEST PASS           ----
UVM_INFO hdl/mem_base_test.sv(56) @ 25000: uvm_test_top [mem_wr_rd_test] ---------------------------------------
UVM_INFO /tools/uvm/ieee_uvm_1800.2_2017/src/base/uvm_report_server.svh(864) @ 25000: reporter [UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity
UVM_INFO :   11
UVM_WARNING :   24
UVM_ERROR :    0
UVM_FATAL :    0
** Report counts by id
[NO_DPI_TSTNAME]     1
[RNTST]     1
[UVM/COMP/NAME]    24
[UVM/COMP/NAMECHECK]     1
[UVM/RELNOTES]     1
[mem_scoreboard]     4
[mem_wr_rd_test]     3

- /tools/uvm/ieee_uvm_1800.2_2017/src/base/uvm_root.svh:585: Verilog $finish
temp@DESKTOP-VFAU2NT:~/mem-tb$

can you or anyone from your team please try at your end running mem-tb example and let me know if it works.

command used: make all

[opensource-elearning]

Also I can see more sv-test test cases are failing before 3 months and now more tests are passing may be because some issue bug and fixes has been made to verilator.

[tgorochowik]

That's correct, the test you mention does not work with upatched mainline Verilator, this is also reflected in the report generated in this repo (https://antmicro.github.io/verilator-verification-features-tests/log.html#s1-s15-t1)

[opensource-elearning]

Dear @tgorochowik,

I would like to express my gratitude for your assistance in reviewing this issue. Unfortunately, we have discovered that mem-tb and uvm-tests are currently not functional.

Would it be possible for you to kindly request a member of your team to address this issue? The entire UVM is currently experiencing difficulties as a result of this issue. Your assistance in resolving this matter would be greatly appreciated.

[opensource-elearning]

@tgorochowik ,

You have been very supportive and cooperative throughout this issue and I am grateful for your assistance. I have a small favor to ask you. Could you or any of your team members kindly address the uvm-tb/mem-tb issue and resolve it at the earliest? It is a critical issue that affects our project's quality and timeline. I would really appreciate your help and expertise on this matter. Thank you.

[mgielda]

Hi @opensource-elearning - for commercial support, please reach out with your company email to contact@antmicro.com and we will take it from there.

[opensource-elearning]

Hi @mgielda,

Thank you for your response. We understand the need for commercial support and appreciate your willingness to provide it.

However, as university students, we do not currently have the financial resources to engage in commercial support. If we had the necessary funds, we would have considered other commercial options such as VCS, Xcellium, or Mentor.

In light of this, we kindly request that you reconsider your comment on issue https://github.com/verilator/verilator/issues/1538.

We would be grateful if you (@tgorochowik) could remove or update your comment https://github.com/verilator/verilator/issues/1538#issuecomment-1832158033 to reflect our current situation. We believe that this would be a more accurate representation of our needs and would allow us to continue to benefit from the support of the open-source community.

Thank you for your understanding and support.