kgugala
commented
5 months ago Hi @yesilzeytin this feature is still being polished and is not yet merged into upstream Verilator, so the results in the SV Tests did not pick this up yet (as the tests there are run against upstream code).
Blog note points to a PR adding this functionality. You can track the progress there and if you'd like to start using the feature before it is merged you can build Verilator from the branch used in the PR, but keep in mind it will change as it is actively developed.
yesilzeytin
Hi,
I have come back here after reading your latest blog post to check on the current state of the verification features. However, when I looked through the commit logs of Verilator and Antmicro Verilator, I couldn't find a specific commit regarding this update. Anyway, I pulled the latest version of this repository and started testing. However, it currently looks like there are no improvements in the randomization, and other UVM features have been degraded.
The test results from February 2023 are as follows (I included an additional test in the suite manually, so don't mind the additional test named under "uvm-custom"):
And here are the results from the current build:
The current results seem to be mostly in line with your shared up-to-date results provided in this link. However, I observe that the report here has two additional "randomize-constraints" tests passing: constraint_soft_multiple_relax.sv and constraint_relax_fail.sv
I have attempted to:
However, these didn't affect the outcomes. Is there something that I miss, or is this a current work in progress that I should wait for some further updates to examine Verilator behavior in constrained randomization?