I am here following the guidance of the blog "https://antmicro.com/blog/2023/10/running-simple-uvm-testbenches-in-verilator/" from the antmicro website. It would be quite cool if I could run UVM in Verilator and I want to dive deeper into the code and check where the gap between uvm and verilator still lies. But the first step...
It seems like the project has been updated and I noticed unfortunately the ReadMe.md is also out of date. So could anyone please provide a quick start instruction for a simple testbench running with uvm? Like the simple memory read/write test case, shown in the website.
Hi, guys
I am here following the guidance of the blog "https://antmicro.com/blog/2023/10/running-simple-uvm-testbenches-in-verilator/" from the antmicro website. It would be quite cool if I could run UVM in Verilator and I want to dive deeper into the code and check where the gap between uvm and verilator still lies. But the first step...
It seems like the project has been updated and I noticed unfortunately the ReadMe.md is also out of date. So could anyone please provide a quick start instruction for a simple testbench running with uvm? Like the simple memory read/write test case, shown in the website.
BR, Yilou