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antmicro / yosys

Yosys Open SYnthesis Suite
http://www.clifford.at/yosys/
ISC License
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Quicklogic timings #7

Open Ravenslofty opened 3 years ago

Ravenslofty commented 3 years ago

My present goal here is to bring up ABC9 support for QuickLogic, which should be a noticeable performance increase.

However, ABC9 needs timings, and at the moment I can only find that data for EOS S3 and PolarPro 3E. This leaves the ArcticPro 2 and 3 without accessible timing data.

Could somebody talk to QL about getting that data available?

cc @kgugala & @mkurc-ant

mkurc-ant commented 3 years ago

That is true. To my knowledge no timing data for AP3 exists. Also both AP2 and AP3 documentation haven't been publicly released yet. Probably you can start with a fake "unit delay" for both architectures.

mkurc-ant commented 3 years ago

@Ravenslofty So as I've stated above: Neither AP2 nor AP3 cell timing data is public yet. You may try using fake timing data (roughly based on PP3). When you do that please add a comment that the data is fake and needs to be replaced in the future.

Ravenslofty commented 3 years ago

So, I've been going through the PP3 timing data provided by QuickLogic, and it doesn't suit my needs very well.

From ABC9's point of view, there's a simple delay between an input and an output. However, the PP3 data file contains unateness information, making it quite difficult to extract the worst-case delay between two points. Additionally, I'm not familiar enough with Liberty files to tell how to calculate that delay (for example, do I just use the non-unate intrinsic delays? Should I add the rise/fall transition times to that?).

mkurc-ant commented 3 years ago

You may look at the library that is used for converting Liberty files to SDF files: https://github.com/QuickLogic-Corp/quicklogic-timings-importer. It is used in SymbiFlow where we import timings from SDF to the FPGA architecture definition. Some simplification of the timing data is done there.

mkurc-ant commented 3 years ago

@Ravenslofty This is the SDF file that is used for LUT cell timing in SymbiFlow: LOGIC_ss_0p990v_m040c.sdf.txt. It was generates from the corresponding Liberty file using the timings-importer that I've mentioned in my previous comment. You may find it helpful.

There are no conditional timings in the SDF. Basically timings-importer generates a new CELLTYPE for each condition outcome. So for example LOGIC3_FS_EQ_0 is LOGIC3 when FS == 0.