Open sasi8985 opened 3 years ago
Vivado Simulator does not support several features of VHDL 2008 and it's lacking some of VHDL 1993. Therefore, it's better to use any other simulator with proper language support. See #242.
Alternatively, you can try converting the sources to Verilog through ghdl --synth
. See https://ghdl.github.io/ghdl/using/Synthesis.html#cmdoption-ghdl-out.
I wanted to simulate the core to view wave forms of different instructions. But i am struck. I am getting this error "FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition from which it cannot recover. Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support."
I created a System Verilog testbench file and instantiated core.vhdl first to see whether at least clock runs or not at my end but i got above error. I am attaching log files. xvhdl.log xvlog.log elaborate.log webtalk.log compile.log Tcl_console_output.txt![Capture_3567](https://user-images.githubusercontent.com/81016256/119966860-5b897980-bfc9-11eb-829f-ffe82f7864be.PNG)
Here is the code : -
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` Also i wanted to know if there is an SV verification requirement. Thanks in advance