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aoeldemann / fluent10g

Programmable FPGA-based Network Tester for Multi-10-Gigabit Ethernet
MIT License
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Error in building the project: IP definition not found #6

Open MengyueSU opened 2 years ago

MengyueSU commented 2 years ago

Hi, I tried to build the project following the start guide, but the Hardware bitstream generation part return an error showing below. When I run commend make -C $FLUENT10G/src hw It finally stop with ERROR: [BD 5-390] IP definition not found for VLNV: TUMLIS:TUMLIS:nt_10g_if_shared:1.00 For more detail:

## }
# create_hier_cell_pcie [current_bd_instance .] pcie_0
create_bd_cell: Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 2583.547 ; gain = 0.023 ; free physical = 27188 ; free virtual = 37576
WARNING: [BD 41-1306] The connection to interface pin </pcie_0/util_ds_buf_0/IBUF_DS_P> is being overridden by the user with net <pcie_sysclk_p_1>. This pin will not be connected as a part of interface connection <CLK_IN_D>.
WARNING: [BD 41-1306] The connection to interface pin </pcie_0/util_ds_buf_0/IBUF_DS_N> is being overridden by the user with net <pcie_sysclk_n_1>. This pin will not be connected as a part of interface connection <CLK_IN_D>.
WARNING: [BD 41-1306] The connection to interface pin </pcie_0/xdma_0/pci_exp_rxn> is being overridden by the user with net <pcie_7x_mgt_rxn_1>. This pin will not be connected as a part of interface connection <pcie_mgt>.
WARNING: [BD 41-1306] The connection to interface pin </pcie_0/xdma_0/pci_exp_rxp> is being overridden by the user with net <pcie_7x_mgt_rxp_1>. This pin will not be connected as a part of interface connection <pcie_mgt>.
WARNING: [BD 41-1306] The connection to interface pin </pcie_0/xdma_0/pci_exp_txn> is being overridden by the user with net <xdma_0_pci_exp_txn>. This pin will not be connected as a part of interface connection <pcie_mgt>.
WARNING: [BD 41-1306] The connection to interface pin </pcie_0/xdma_0/pci_exp_txp> is being overridden by the user with net <xdma_0_pci_exp_txp>. This pin will not be connected as a part of interface connection <pcie_mgt>.
# create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 \
#   axi_interconnect_0
# set_property -dict [list  CONFIG.NUM_SI {9} CONFIG.NUM_MI {2} \
#                           CONFIG.ENABLE_ADVANCED_OPTIONS {1} \
#                           CONFIG.XBAR_DATA_WIDTH {512}] \
#   [get_bd_cells axi_interconnect_0]
# create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 \
#   axi_interconnect_1
# set_property -dict [list CONFIG.NUM_SI {1} CONFIG.NUM_MI {27}] \
#   [get_bd_cells axi_interconnect_1]
# create_bd_cell -type ip -vlnv TUMLIS:TUMLIS:nt_10g_if_shared:1.00 if_0
ERROR: [BD 5-390] IP definition not found for VLNV: TUMLIS:TUMLIS:nt_10g_if_shared:1.00 
ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.

    while executing
"create_bd_cell -type ip -vlnv TUMLIS:TUMLIS:nt_10g_if_shared:1.00 if_0"
    (file "tcl/fluent10g_create.tcl" line 94)
INFO: [Common 17-206] Exiting Vivado at Mon Dec 20 17:09:40 2021...

But I verified that the IP nt_10g_if_shared is successfully built before:

make[2]: Leaving directory `/users/su/Documents/fluent10g/src/hardware/ip/nt_10g_if'
make[2]: Entering directory `/users/su/Documents/fluent10g/src/hardware/ip/nt_10g_if_shared'
vivado -mode batch -source $(basename `pwd`).tcl

****** Vivado v2020.2.2 (64-bit)
  **** SW Build 3118627 on Tue Feb  9 05:13:49 MST 2021
  **** IP Build 3115676 on Tue Feb  9 10:48:11 MST 2021
    ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.

source nt_10g_if_shared.tcl
# set design nt_10g_if_shared
# set top nt_10g_if_shared
# source ../ip_create_start.tcl
## set device xc7vx690t-3-ffg1761
## set proj_dir ./ip_project
## set ip_version 1.00
## create_project -name ${design} -force -dir "./${proj_dir}" -part ${device} -ip
## set_property source_mgmt_mode ALL [current_project]
## set_property top ${top} [current_fileset]
# read_verilog "./hdl/nt_10g_if_shared.v"
# ipx::package_project -force -import_files
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/CMC/tools/xilinx/Vitis_2020.2/Vivado/2020.2/data/ip'.
INFO: [IP_Flow 19-5107] Inferred bus interface 'm_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axis' of definition 'xilinx.com:interface:axis:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'reset' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'reset_counter_done_out' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3158] Bus Interface 'm_axis': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
WARNING: [IP_Flow 19-3158] Bus Interface 's_axis': FREQ_HZ bus parameter missing from AXI interface when interface is not associated to a clock.
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
# ipx::infer_bus_interface clk156_out xilinx.com:signal:clock_rtl:1.0 \
#   [ipx::current_core]
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk156_out' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
INFO: [IP_Flow 19-4728] Bus Interface 'clk156_out': Added interface parameter 'ASSOCIATED_RESET' with value 'reset_counter_done_out'.
# ipx::infer_bus_interface areset_clk156_out xilinx.com:signal:reset_rtl:1.0 \
#   [ipx::current_core]
INFO: [IP_Flow 19-5107] Inferred bus interface 'areset_clk156_out' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
# ipx::add_bus_parameter FREQ_HZ [ipx::get_bus_interfaces m_axis -of_objects \
#   [ipx::current_core]]
# ipx::add_bus_parameter FREQ_HZ [ipx::get_bus_interfaces s_axis -of_objects \
#   [ipx::current_core]]
# ipx::add_bus_parameter FREQ_HZ [ipx::get_bus_interfaces clk156_out -of_objects \
#   [ipx::current_core]]
# set_property value 156250000 [ipx::get_bus_parameters FREQ_HZ -of_objects \
#   [ipx::get_bus_interfaces clk156_out -of_objects [ipx::current_core]]]
# ipx::add_bus_parameter ASSOCIATED_BUSIF \
#   [ipx::get_bus_interfaces clk156_out -of_objects [ipx::current_core]]
# set_property value m_axis:s_axis \
#   [ipx::get_bus_parameters ASSOCIATED_BUSIF -of_objects \
#   [ipx::get_bus_interfaces clk156_out -of_objects [ipx::current_core]]]
# source ../ip_create_end.tcl
## update_compile_order -fileset sources_1
## update_compile_order -fileset sim_1
## set_property name ${design} [ipx::current_core]
## set_property library {TUMLIS} [ipx::current_core]
## set_property vendor_display_name {TUMLIS-aoeldemann} [ipx::current_core]
## set_property company_url {https://www.lis.ei.tum.de} [ipx::current_core]
## set_property vendor {TUMLIS} [ipx::current_core]
## set_property supported_families {{virtex7} {Production}} [ipx::current_core]
## set_property version ${ip_version} [ipx::current_core]
## set_property display_name ${design} [ipx::current_core]
## set_property description ${design} [ipx::current_core]
## ipx::infer_user_parameters [ipx::current_core]
## ipx::check_integrity [ipx::current_core]
INFO: [IP_Flow 19-7067] Note that bus interface 'm_axis' has a fixed FREQ_HZ of ''. This value will be respected whenever this IP is instantiated in IP Integrator.
INFO: [IP_Flow 19-7067] Note that bus interface 's_axis' has a fixed FREQ_HZ of ''. This value will be respected whenever this IP is instantiated in IP Integrator.
INFO: [IP_Flow 19-7067] Note that bus interface 'clk156_out' has a fixed FREQ_HZ of '156250000'. This value will be respected whenever this IP is instantiated in IP Integrator.
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed.
## ipx::save_core [ipx::current_core]
## close_project
INFO: [Common 17-206] Exiting Vivado at Mon Dec 20 17:00:49 2021...
make[2]: Leaving directory `/users/su/Documents/fluent10g/src/hardware/ip/nt_10g_if_shared'
make[2]: Entering directory `/users/su/Documents/fluent10g/src/hardware/ip/nt_ctrl'

Thank you.

aoeldemann commented 2 years ago

Hi! Sorry for my late reply. Did you manage to make progress with building the bitstream? If not, could you please provide the full output of the make -C $FLUENT10G/src hw output?

I suspect that it may be a problem with the Xilinx MAC IP core. The design was initially built and synthesized with Vivado 2018.3 and I see that you are using Vivado 2020.2.2. I'm not sure whether the axi_10g_ethernet IP core is still at version v3.1 in Vivado 2020.2.2. If not, the design would need to be adjusted. Would it be possible for you to build the design with Vivado 2018.3?

MengyueSU commented 2 years ago

Thank you for your answer and I apologize for the delay. Please check the output file: https://drive.google.com/file/d/1WHCmDiG--_dquZNkwkUtzxxza1zrMnaK/view?usp=sharing And we will try to install the version 2018.3. Thanks.

aoeldemann commented 2 years ago

Hi! Could you please attach the file here or create a pastebin? Don't have access to Google Docs right now. Thanks so much!

BR, Andreas

anmomu92 commented 2 years ago

I had the exact same issue. Installing Vivado version 2018.3 solved it.