search

aolofsson / oh

Verilog library for ASIC and FPGA designers
MIT License
1.17k stars 285 forks source link

spi: master doesn't transfer 2 MSB in data byte #84

Open olajep opened 8 years ago

olajep commented 8 years ago

Test case: fclk0 = 25 MHz clkdiv=254 sclk = 100 kHz

  1. Master writes 0xff to SPI_USER0
  2. Master reads data from SPI_USER0

As seen in the waveform capture master does not transfer the two most significant bits in the data byte. This does not seem to happen in simulation.

spi-high-bits-gone

waveform.vcd.txt

olajep commented 8 years ago

It also drops the 2 MSB in the command byte.