libm/riscv64: add partial hard-float support to libm

[liushuyu]

Now, riscv64 target correctly supports rint and lrint rounding for float and double (long double is currently unsupported).

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# define __get_fcw(cw) __asm__ volatile ("frcsr %0" : "=r" (cw))
# define __set_fcw(cw) __asm__ volatile ("fscsr %z0" : : "r" (cw))

This segment replaces the older naming convention with the newer ones specified in RISC-V ISA standard manual, version 20191213. Removed per request.

[unicornx]

Please separate this PR into two.

• One is bug-fix, which contains the obsolete alias frsr/fssr bug in fesetround(). BTW, I find according to https://github.com/riscv/riscv-isa-manual/issues/419, due to glibc, all assembler will have to compatible with support this in perpetuity. But anyway, I believe we should fix this in our new code.
• One is optimization to use hard float point to replace soft emulation for float point operation. Regarding this, I need some more time to evaluate and talk with RVI upstream to decide if we need to involve this in for current time.

[liushuyu]

Rename segment removed from this pull request.

[unicornx]

closed because we have resolved this in other PR.