[Tracking Issue] Write schedules for RISC-V targets

[areusch]

We added initial support for RISC-V in microTVM by proving that we can run regression tests against the Zephyr RISC-V target (backed by QEMU). However, we have not yet added support for any V- or P- extension SIMD instructions to provide more interesting performance numbers out of the box. This issue tracks adding those schedules, which involves:

• [ ] selecting a simulator which can correctly execute those instructions
• [ ] adding the schedules
• [ ] adding tests to verify functional correctness

[PhilippvK]

I've recently worked with RISC-V vector instructions using these simulators:

• Spike (riscv-isa-sim) - https://github.com/riscv-software-src/riscv-isa-sim
  • Supports V-Ext. (v1.0) and P-Ext. (v0.9.2)
  • No pre-build binaries available - Need to compile simulator (spike) and proxy kernel (pk) from source
  • Debugging support with GDB very limited
• riscvOVPSimPlus - https://www.ovpworld.org/library/wikka.php?wakka=riscvOVPsimPlus
  • Version with V-Ext. support: Sign-up required for download, internet connection for usage
  • However, perfomance and usability is great (Much faster than Spike)

Both of them are only ISS, e.g. not cycle accurate, but that should not be an issue.

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Another thing I would like to point out is that the vectorization support in the RISC-V GCC toolchain seems to be "(References: 1 2 3). Thus, one should switch to using LLVM/Clang instead (LLVM also supports all RVV intrinsics).