Change default sample rate from ~96khz to ~48kHz and BICK from 12MHz -> 6MHz which improves stability a bit with long cables from FPGA/PMOD. There is no audible difference and the noise is a bit lower.
Clean up clocking architecture so we can select any sample rate from 8kHz to 48kHz, removing fixed 12MHz assumptions everywhere.
Rewrite AK4619 driver to collapse most of the logic into one posedge block on clk_256fs.
Some other minor fixes so that this repository plays better with LiteX (splitting out the wavetable osc as its own module, bubbling up .hex config paths).
TESTED on all supported platforms.