Implement cache line bursting in WishboneL2Cache. This component is used by DelayLine to reduce PSRAM transactions.
Experimentally, for delay lines with 1-2 taps, a cache size of 64 words with 4 word bursts (4 words per line) seems to perform best. So this is the default. Seems to use about 0.3x of the memory bandwidth relative to no bursting (in simulation).
Modify PSRAM simulation to also simulate 8-cycle DATAVALID delay returned by ECP5 DQS hard blocks.
Clean up UnusedElaboratable warnings in DSP examples by only instantiating PSRAM if the core actually needs it
Update wishbone signature of cache, raster to match what those busses actually support
Remove test_cache.py, test_delayln.py is already a more useful test anyway.
WishboneL2Cache. This component is used byDelayLineto reduce PSRAM transactions.test_cache.py,test_delayln.pyis already a more useful test anyway.