The System V ABI on i386 defines long long (i.e., int64_t, i.e., Swift's Int64) to have size 8 but alignment 4, while the package assumes that integer types always have their alignment match their size.
This means that the package is issuing potentially misaligned double-wide atomic operations. We do not want that.
Accesses to cacheable memory that are split across cache lines and page boundaries are not guaranteed to be atomic by the Intel Core 2 Duo, Intel® AtomTM, Intel Core Duo, Pentium M, Pentium 4, Intel Xeon, P6 family, Pentium, and Intel486 processors. The Intel Core 2 Duo, Intel Atom, Intel Core Duo, Pentium M, Pentium 4, Intel Xeon, and P6 family processors provide bus control signals that permit external memory subsystems to make split accesses atomic; however, nonaligned data accesses will seriously impact the performance of the processor and should be avoided.
(from Intel® 64 and IA-32 Architectures Software Developer’s Manual, section 8.1.1., Guaranteed Atomic Operations.)
The package should use explicit @_alignment attributes on the atomic storage types to avoid these problems.
The System V ABI on i386 defines
long long(i.e.,int64_t, i.e., Swift'sInt64) to have size 8 but alignment 4, while the package assumes that integer types always have their alignment match their size.This means that the package is issuing potentially misaligned double-wide atomic operations. We do not want that.
The package should use explicit
@_alignmentattributes on the atomic storage types to avoid these problems.