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various u-boot patches
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about h616/h313 emmc boot #7

Open sputnik2019 opened 3 years ago

sputnik2019 commented 3 years ago

I designed an h313 board，I can use the sd card boot uboot and linux ，in linux i tested emmc driver it is ok 。it can work steadily for hs200，but when i use emmc boot，spl boot but uart print : mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices

ERROR ### Please RESET the board

and debug info:

U-Boot SPL 2021.01-rc5-armbian (Apr 26 2021 - 04:47:20 -0700) DRAM:testing 32-bit width, rank = 2 read calibration failed! testing 32-bit width, rank = 1 read calibration failed! testing 16-bit width, rank = 2 read calibration failed! testing 16-bit width, rank = 1//wo use 16bit ddr3 MBUS port 0 cfg0 0100000d cfg1 00640080 MBUS port 1 cfg0 06000009 cfg1 01000578 MBUS port 2 cfg0 0200000d cfg1 00600100 MBUS port 3 cfg0 01000009 cfg1 00500064 MBUS port 4 cfg0 20000209 cfg1 1388157c MBUS port 5 cfg0 00640209 cfg1 00200040 MBUS port 6 cfg0 00640209 cfg1 00200040 MBUS port 8 cfg0 01000009 cfg1 00400080 MBUS port 11 cfg0 01000009 cfg1 00640080 MBUS port 14 cfg0 04000009 cfg1 00400100 MBUS port 16 cfg0 2000060d cfg1 09600af0 MBUS port 21 cfg0 0800060d cfg1 02000300 MBUS port 25 cfg0 0064000d cfg1 00200040 MBUS port 26 cfg0 20000209 cfg1 1388157c MBUS port 37 cfg0 01000009 cfg1 00400080 MBUS port 38 cfg0 00640209 cfg1 00200040 MBUS port 39 cfg0 20000209 cfg1 1388157c MBUS port 40 cfg0 00640209 cfg1 00200040 512 MiB SPL malloc() before relocation used 0x0 bytes (0 KB)

SPL: board_init_r() Trying to boot from MMC2 init mmc 0 resource init mmc 0 clock and io mmc 0 set mod-clk req 24000000 parent 24000000 n 1 m 1 rate 24000000 size=x, ptr=1a0, limit=1a0: 4fd00000 init mmc 2 resource init mmc 2 clock and io mmc 2 set mod-clk req 24000000 parent 24000000 n 1 m 1 rate 24000000 size=x, ptr=1a0, limit=340: 4fd001a0 clock is disabled (0Hz) set ios: bus_width: 0, clock: 0 set ios: bus_width: 1, clock: 0 clock is enabled (400000Hz) set ios: bus_width: 1, clock: 400000 mmc 2 set mod-clk req 400000 parent 24000000 n 4 m 15 rate 400000 CMD_SEND:0 ARG 0x00000000 mmc 2, cmd 0(0x80008000), arg 0x00000000 mmc resp 0x00000000 MMC_RSP_NONE CMD_SEND:8 ARG 0x000001aa mmc 2, cmd 8(0x80000148), arg 0x000001aa cmd timeout 100 RET -110 CMD_SEND:55 ARG 0x00000000 mmc 2, cmd 55(0x80000177), arg 0x00000000 cmd timeout 100 RET -110 CMD_SEND:0 ARG 0x00000000 mmc 2, cmd 0(0x80008000), arg 0x00000000 mmc resp 0x00000000 MMC_RSP_NONE CMD_SEND:1 ARG 0x00000000 mmc 2, cmd 1(0x80000041), arg 0x00000000 mmc resp 0x00ff8080 MMC_RSP_R3,4 0x00ff8080 CMD_SEND:1 ARG 0x40300000 mmc 2, cmd 1(0x80000041), arg 0x40300000 mmc resp 0x00ff8080 MMC_RSP_R3,4 0x00ff8080 CMD_SEND:1 ARG 0x40300000 mmc 2, cmd 1(0x80000041), arg 0x40300000 mmc resp 0x00ff8080 MMC_RSP_R3,4 0x00ff8080 CMD_SEND:1 ARG 0x40300000 mmc 2, cmd 1(0x80000041), arg 0x40300000 mmc resp 0xc0ff8080 MMC_RSP_R3,4 0xc0ff8080 CMD_SEND:2 ARG 0x00000000 mmc 2, cmd 2(0x800001c2), arg 0x00000000 mmc resp 0xa27646c1 0x3002a021 0x30344741 0x11010030 MMC_RSP_R2 0x11010030 0x30344741 0x3002a021 0xa27646c1 

                                    DUMPING DATA
                                    000 - 11 01 00 30 
                                    004 - 30 34 47 41 
                                    008 - 30 02 a0 21 
                                    012 - a2 76 46 c1

CMD_SEND:3 ARG 0x00010000 mmc 2, cmd 3(0x80000143), arg 0x00010000 mmc resp 0x00000500 MMC_RSP_R1,5,6,7 0x00000500 CMD_SEND:9 ARG 0x00010000 mmc 2, cmd 9(0x800001c9), arg 0x00010000 mmc resp 0x924000e3 0xffffffe7 0x0f5903ff 0xd05e0032 MMC_RSP_R2 0xd05e0032 0x0f5903ff 0xffffffe7 0x924000e3 

                                    DUMPING DATA
                                    000 - d0 5e 00 32 
                                    004 - 0f 59 03 ff 
                                    008 - ff ff ff e7 
                                    012 - 92 40 00 e3

CMD_SEND:7 ARG 0x00010000 mmc 2, cmd 7(0x80000147), arg 0x00010000 mmc resp 0x00000700 MMC_RSP_R1,5,6,7 0x00000700 CMD_SEND:8 ARG 0x00000000 mmc 2, cmd 8(0x80002348), arg 0x00000000 trans data 512 bytes cacl timeout 78 msec mmc resp 0x00000900 MMC_RSP_R1,5,6,7 0x00000900 size=x, ptr=200, limit=540: 4fd00340 CMD_SEND:6 ARG 0x03af0100 mmc cmd 6 check rsp busy mmc 2, cmd 6(0x80000146), arg 0x03af0100 mmc resp 0x00000800 MMC_RSP_R1b 0x00000800 CMD_SEND:13 ARG 0x00010000 mmc 2, cmd 13(0x8000014d), arg 0x00010000 mmc resp 0x00000900 MMC_RSP_R1,5,6,7 0x00000900 CURR STATE:4 clock is enabled (25000000Hz) set ios: bus_width: 1, clock: 25000000 mmc 2 set mod-clk req 25000000 parent 588000000 n 2 m 12 rate 24500000 CMD_SEND:6 ARG 0x03b70200 mmc cmd 6 check rsp busy mmc 2, cmd 6(0x80000146), arg 0x03b70200 mmc resp 0x00000800 MMC_RSP_R1b 0x00000800 CMD_SEND:13 ARG 0x00010000 mmc 2, cmd 13(0x8000014d), arg 0x00010000 mmc resp 0x00000900 MMC_RSP_R1,5,6,7 0x00000900 CURR STATE:4 set ios: bus_width: 8, clock: 25000000 mmc 2 set mod-clk req 25000000 parent 588000000 n 2 m 12 rate 24500000 CMD_SEND:6 ARG 0x03b90100 mmc cmd 6 check rsp busy mmc 2, cmd 6(0x80000146), arg 0x03b90100 mmc resp 0x00000800 MMC_RSP_R1b 0x00000800 CMD_SEND:13 ARG 0x00010000 mmc 2, cmd 13(0x8000014d), arg 0x00010000 mmc resp 0x00000900 MMC_RSP_R1,5,6,7 0x00000900 CURR STATE:4 CMD_SEND:8 ARG 0x00000000 mmc 2, cmd 8(0x80002348), arg 0x00000000 trans data 512 bytes cacl timeout 78 msec mmc resp 0x00000900 MMC_RSP_R1,5,6,7 0x00000900 clock is enabled (52000000Hz) set ios: bus_width: 8, clock: 52000000 mmc 2 set mod-clk req 52000000 parent 588000000 n 1 m 12 rate 49000000 CMD_SEND:8 ARG 0x00000000 mmc 2, cmd 8(0x80002348), arg 0x00000000 trans data 512 bytes cacl timeout 78 msec mmc resp 0x00000900 MMC_RSP_R1,5,6,7 0x00000900 spl: mmc boot mode: raw CMD_SEND:16 ARG 0x00000200 mmc 2, cmd 16(0x80000150), arg 0x00000200 mmc resp 0x00000900 MMC_RSP_R1,5,6,7 0x00000900 CMD_SEND:17 ARG 0x00000070 mmc 2, cmd 17(0x80002351), arg 0x00000070 trans data 512 bytes cacl timeout 78 msec mmc resp 0x00000900 MMC_RSP_R1,5,6,7 0x00000900 hdr read sector 70, count=1 Found FIT CMD_SEND:16 ARG 0x00000200 mmc 2, cmd 16(0x80000150), arg 0x00000200 mmc resp 0x00000900 MMC_RSP_R1,5,6,7 0x00000900 CMD_SEND:18 ARG 0x00000070 mmc 2, cmd 18(0x80003352), arg 0x00000070 trans data 710144 bytes cmd timeout 180 RET -110 fit read sector 70, sectors=1387, dst=49f52840, count=0, size=0xad5a8 mmc_load_image_raw_sector: mmc block read error spl: mmc boot mode: fs SPL: failed to boot from all boot devices

ERROR ### Please RESET the board

apritzel commented 3 years ago

I didn't go through the whole log yet, just to check one thing: Did you apply the patch I send the other day? https://lists.denx.de/pipermail/u-boot/2021-April/448093.html And does access to the eMMC work in U-Boot when you boot from SD card, then use the mmc or any filesystem command? I just got an H616 TV box with eMMC, but didn't try eMMC boot yet, just fixed eMMC access from U-Boot proper.

apritzel commented 3 years ago

So looking through the log it doesn't look too bad, does it? It reads one sector at 0x70, which is right behind the SPL. And it detects a FIT image header in there. And then it tries to read the rest of the FIT (~700KB), which sounds like a reasonable size. So it reads something sensible, but then times out when reading more sectors? Also to make sure: Did you write u-boot-sunxi-with-spl.bin to sector 16 of the eMMC data partition? Or was that in the boot partition?

sputnik2019 commented 3 years ago

ths，I patched pinmux and sunxi_mmc.c. I found that as long as the load big file (>500KB)is wrong ,when sd card boot i tested emmc ，the problem remains。Eventually, I found that adjusting the emmc clock（<10M）,it is work!My guess is that the delay is not set correctly for driver！

apritzel commented 3 years ago

I see what you mean: I can read the partition table and list directories just fine, but when loading more than 6 sectors I get the error as well: => mmc read $kernel_addr_r 10 6 MMC read: dev # 1, block # 16, count 6 ... 6 blocks read: OK => mmc read $kernel_addr_r 10 7 MMC read: dev # 1, block # 16, count 7 ... 0 blocks read: ERROR

That's somewhat odd, since I don't remember us having issues with eMMC in U-Boot in the past, and the timing is conservative anyway: We use "High Speed DDR" (at 50 MHz), that should be most compatible.

Which clock did you adjust, exactly? Did you change cfg->f_max? I will have a closer look later, maybe some clocks are set up wrongly? (We have seen clock doubling before)

sputnik2019 commented 3 years ago

yes，i changed cfg->f_max to 12Mhz.

jmsvigno commented 1 year ago

I have an problem with Internal Boot on H616, iI install linux on emmc on H616, but when boot, says this message: U-Boot SPL 2023.10-00649-gbe2abe73df-dirty (Nov 01 2023 - 13:17:36 -0300) DRAM: 1024 MiB Trying to boot from MMC2 MMC Device 1 not found spl: could not find mmc device 1. error: -19 SPL: failed to boot from all boot devices

can anyone help me? ps: I think it's an edition in dtb or h616.dtsi, but which one would it be???

jmsvigno commented 1 year ago

I have an problem with Internal Boot on H616, iI install linux on emmc on H616, but when boot, says this message: U-Boot SPL 2023.10-00649-gbe2abe73df-dirty (Nov 01 2023 - 13:17:36 -0300) DRAM: 1024 MiB Trying to boot from MMC2 MMC Device 1 not found spl: could not find mmc device 1. error: -19 SPL: failed to boot from all boot devices

can anyone help me? ps: I think it's an edition in dtb or h616.dtsi, but which one would it be???

ps: after editing the config with the parameter CONFIG_MMC_SUNXI_SLOT_EXTRA=2 worked, but now this error appears:

mmc_load_image_raw_sector: mmc block read error

apritzel commented 1 year ago

@jmsvigno yes, this is the same problem as described above: at the moment reading more than a few blocks from eMMC on an H616 system in U-Boot does not work. You can try to play around with the clock, as suggested above by @sputnik2019, though this sounds like a hack. I wonder if adding some delay after reading a few blocks helps? Also I think someone reported that using DMA instead of pulling words from the FIFO would work. At the moment I don't have time to look into this, but feel free to ask for help in a wider forum, for instance on the U-Boot or sunxi mailing list or IRC channel.

jmsvigno commented 1 year ago

@jmsvigno yes, this is the same problem as described above: at the moment reading more than a few blocks from eMMC on an H616 system in U-Boot does not work. You can try to play around with the clock, as suggested above by @sputnik2019, though this sounds like a hack. I wonder if adding some delay after reading a few blocks helps? Also I think someone reported that using DMA instead of pulling words from the FIFO would work. At the moment I don't have time to look into this, but feel free to ask for help in a wider forum, for instance on the U-Boot or sunxi mailing list or IRC channel.

@apritzel below are the boot messages from the original android:

[125]BOOT0 commit : 904a4b2 [128]set pll start [130]periph0 has been enabled [134]set pll end [135]unknow PMU [137]PMU: AXP806 [144]vaild para:8 select dram para2 [148]board init ok [150]DRAM BOOT DRIVE INFO: V0.60 [153]the chip id is 0x5d00 [156]chip id check OK [158]DRAM_VCC set to 1200 mv [163][AUTO DEBUG]32bit,2 ranks training success! [173]DRAM CLK =720 MHZ [175]DRAM Type =7 (3:DDR3,4:DDR4,7:LPDDR3,8:LPDDR4) [183]Actual DRAM SIZE =1024 M [186]DRAM SIZE =1024 MBytes, para1 = 30ea, para2 = 4001000, dram_tpr13 = 6061 [199]DRAM simple test OK. [201]rtc standby flag is 0x0, super standby flag is 0x0 [207]dram size =1024 [210]card no is 2 [211]sdcard 2 line count 8 [214][mmc]: mmc driver ver 2019-12-19 10:41 [218][mmc]: set f_max to 50M, set f_max_ddr to 50M [223][mmc]: mmc 2 bias 4 [231][mmc]: Try MMC card 2 [291][mmc]: MMC 5.0 [293][mmc]: HSDDR52/DDR50 8 bit [296][mmc]: 50000000 Hz [299][mmc]: 7296 MB [301][mmc]: SD/MMC 2 init OK!!! [363]Loading boot-pkg Succeed(index=0). [367]Entry_name = u-boot [376]Entry_name = monitor [379]Entry_name = dtbo [382]Entry_name = dtb [386]tunning data addr:0x4a0003e8 [389]Jump to second Boot. NOTICE: BL3-1: v1.0(debug):cfcc355 NOTICE: BL3-1: Built : 19:08:45, 2020-11-17 NOTICE: BL3-1 commit: 8 ERROR: Error initializing runtime service tspd_fast NOTICE: BL3-1: Preparing for EL3 exit to normal world NOTICE: BL3-1: Next image address = 0x4a000000 NOTICE: BL3-1: Next image spsr = 0x1d3

U-Boot 2018.05 (May 14 2021 - 10:23:10 +0800) Allwinner Technology

[00.464]CPU: Allwinner Family [00.466]Model: sun50iw9 I2C: ready [00.471]DRAM: 1 GiB [00.474]Relocation Offset is: 35ec5000 [00.511]secure enable bit: 0 [00.514]pmu_axp152_probe pmic_bus_read fail [00.518]PMU: AXP806 [00.522]CPU=1008 MHz,PLL6=600 Mhz,AHB=200 Mhz, APB1=100Mhz MBus=400Mhz [00.709]sunxi overlay merged okqv [00.712]drv_disp_init [00.742]__clk_enable: clk is null. [00.748]drv_disp_init finish [00.751]gic: sec monitor mode [00.773]flash init start [00.775]workmode = 0,storage type = 2 [00.778]MMC: 2 [00.780]get mem for descripter OK ! [00.789]get sdc2 sdc_boot0_sup_1v8 fail. [00.793]io is 1.8V 00.869]sunxi flash init ok [00.873]Loading Environment from SUNXI_FLASH... OK [00.884]usb burn from boot delay time 0 weak:otg_phy_config [00.897]usb prepare ok [01.700]overtime [01.704]do_burn_from_boot usb : no usb exist [01.708]boot_gui_init:start FAT: Misaligned buffer address (7be81e78) 32 bytes read in 4 ms (7.8 KiB/s) [01.993]boot_gui_init:finish [01.996]bmp_name=bootlogo.bmp 3686456 bytes read in 35 ms (100.4 MiB/s) [02.044]hsddr 2-50000000 [02.046]hs200 5-200000000 [02.049]get max-frequency ok 100000000 Hz [02.053]0 1 0: 0 1 0 [02.055]delete mmc-hs400-1_8v from dtb [02.061]update dts