Closed ikwzm closed 8 years ago
Hello,
Sorry, it does not implement for return value. Now, during the implement. Please, wait.
Hidemi Ishihara.
On Fri, 13 Nov 2015 21:56:32 -0800 KAWAZOME Ichiro notifications@github.com wrote:
// fib.c int fib(int n) { int r0 = 0; int r1 = 1; int i; if (n <= 0) return 0; if (n == 1) return 1; for(i = 0; i < n; i++) { int prev_r1 = r1; r1 = r0 + r1; r0 = prev_r1; } return r0; }
generate from fib.c to fib.v
shell% synverll fib.c fib_top
verilog-hdl like the following is generated.
// fib.v module fib( input __func_clock, input __func_reset, input __func_start, output reg __func_done, output reg __func_ready, output reg __gm_req, output reg __gm_rnw, input __gm_done, output reg [31:0] __gm_adrs, output reg [1:0] __gm_leng, input [31:0] __gm_di, output reg [31:0] __gm_do, // Memory Singal input [31:0] __args_n, // Call Singal output reg __dummy );
The port for outputting the return value to where?
Reply to this email directly or view it on GitHub: https://github.com/aquaxis/synverll/issues/1
Hidemi Ishihara hidemi@sweetcafe.jp
Hello,
I modify with V0.4.
Best regards,
generate from fib.c to fib.v
verilog-hdl like the following is generated.
The port for outputting the return value to where?