The behaviour of bits 0-3 and 7 in the control/status port were a complete guess and had no reflection in hardware testing. They have been adjusted to match hardware.
The EEPROM interface always writes and reads out 16 bits to/from the EEPROM, including the initial zeroes in the command value. The M93LCx6 code has been updated to support this case in line with the datasheet.
The read and write data port have been separated. This was a detail which every community documentation in existence got wrong, so no worries about that one ^^
Internal EEPROM protection has been implemented.
The handling of invalid control commands (more than one bit set) has been fixed.
Emulation of the 93C46-family internal EEPROM on SPHINX in ASWAN mode has been implemented. In particular, this fixes running any mono WonderSwan game which takes advantage of the internal EEPROM on the WonderSwan Color system's compatibility mode.
All of these changes pass the relevant tests in ws-test-suite (mono/eeprom/internal.ws) both as a WonderSwan and a WonderSwan Color. This isn't 100% accurate (particularly, timing is not reflected; but there are also some questions about more edge case-y behaviour), but it's much closer.
All of these changes pass the relevant tests in ws-test-suite (mono/eeprom/internal.ws) both as a WonderSwan and a WonderSwan Color. This isn't 100% accurate (particularly, timing is not reflected; but there are also some questions about more edge case-y behaviour), but it's much closer.