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aristanetworks / avd

Arista Validated Designs
https://avd.arista.com
Apache License 2.0
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Missing mlag stanza in for server downlink ports #138

Closed titom73 closed 4 years ago

titom73 commented 4 years ago

Issue Type

Summary

When using AVD with server ports configuration for a dual homed on a mlag vtep, mlag stanza is missing

Role or Module Name

arista.avd collection and Python libraries version using devel at a01f0a4

OS / Environment

EOS Version

4.24.0F

Cloudvision version

N/A

Steps to reproduce

From server.yml

servers:
  DCI_RTR01:
    rack: DCI_POD
    adapters:
      - server_ports: [Eth1]
        switch_ports: [Ethernet5]
        switches: [SITE01-BL01A]
        profile: DCI_IX
        port_channel:
          state: present
          description: PortChannel5
          mode: active
      - server_ports: [Eth2]
        switch_ports: [Ethernet5]
        switches: [SITE01-BL01B]
        profile: DCI_IX
        port_channel:
          state: present
          description: PortChannel5
          mode: active

Expected results

interface Port-Channel5
   description POD01-SRV_PortChannel5
   switchport access vlan 110
   mlag 5
!

Actual results

interface Port-Channel5
   description POD01-SRV_PortChannel5
   switchport access vlan 110
!
titom73 commented 4 years ago

Misconfiguration

Fomr @carlbuchmann 

DCI_RTR01:
    rack: DCI_POD
    adapters:
      - server_ports: [Eth1, Eth2]
        switch_ports: [Ethernet5, Ethernet5 ]
        switches: [SITE01-BL01A, SITE01-BL01B]
        profile: DCI_IX
        port_channel:
          state: present
          description: data
          mode: active