arminalaghi / scsynth

Synthesis tool for stochastic computing
MIT License
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Fix for verilog generator #3

Closed danilo-bc closed 5 years ago

danilo-bc commented 5 years ago

The simplest case (degree/degrees = 1) had a bug where structures like wire [-1:0] and 0'd0 0'd1 would appear.

This fixes the ReSC/MReSC modules generated when degree/degrees = 1, making those examples become [0:0] (valid), and 1'd0 and 1'd1.