PTW w/ sv39/sv48
TLB w/ 64 bit addresses
Maybe: Optimize so that top-level tree can be cached?
ALU: 64/32 bit
Regfile: 64 bit version
AXI4 Peripherals need to be ported and tested under 64 bit configuration. BRAM uses address fixed calculation for 32 bit, need to port to 64 bit, etc
Execute: New instructions
Loadgen/Storegen: Support for 64 bit
Brcond: Support for 64 bit
Multiplier/Divider: Support for 64 bit
AXI4 Core surrounding need support for 64 bit bus.
Achieve RV64GC:
FPU: Add the FPU that supports D/F extensions
C extension: Extend current implementation to support 32 bit instructions that are aligned to 16 bit. Maybe implement the instruction cache separately?
PTW w/ sv39/sv48 TLB w/ 64 bit addresses Maybe: Optimize so that top-level tree can be cached? ALU: 64/32 bit Regfile: 64 bit version AXI4 Peripherals need to be ported and tested under 64 bit configuration. BRAM uses address fixed calculation for 32 bit, need to port to 64 bit, etc Execute: New instructions Loadgen/Storegen: Support for 64 bit Brcond: Support for 64 bit Multiplier/Divider: Support for 64 bit AXI4 Core surrounding need support for 64 bit bus.
Achieve RV64GC: FPU: Add the FPU that supports D/F extensions C extension: Extend current implementation to support 32 bit instructions that are aligned to 16 bit. Maybe implement the instruction cache separately?