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armleo / ArmleoCPU

ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set
GNU General Public License v3.0
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Implement CLINT/PLIC #51

Open armleo opened 3 years ago

armleo commented 3 years ago

For CLINT memory map refer to: https://patchwork.kernel.org/project/qemu-devel/patch/1515637324-96034-14-git-send-email-mjc@sifive.com/ And: https://sifive.cdn.prismic.io/sifive%2Fc89f6e5a-cf9e-44c3-a3db-04420702dcc1_sifive+e31+manual+v19.08.pdf

For PLIC refer to: https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc

Note: Bug in AXI4LiteConverter.v for responses for missaligned access

armleo commented 3 years ago

Clint mtime should be storeable "Bug in AXI4LiteConverter.v for responses for missaligned access" fixed

armleo commented 3 years ago

Update: https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc aclint specification is provided here.

TODO: Implement ACLINT instead of CLINT

armleo commented 3 years ago

TODO: Update ACLINT docs so that mtime frequency to be kept low to allow chapter simple "Synchronizing Multiple MTIMER Devices" implementation

armleo commented 3 years ago

ACLINT is done. PLIC need to be implemented.