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arshadri / lzw_systemc

An implementation of LZW encoder in SystemC and verified in FPGA
http://arshadri.github.io/lzw_systemc/
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Failed in Implementation #1

Open kallianisawesome opened 3 years ago

kallianisawesome commented 3 years ago

I can synthesis this program in vivado2018, but I can't run implementation. It says: [DRC INBB-3] Black Box Instances:Cell 'io_ram/i1' of Type 'RAMB4_S8_S8' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully. Can sombody help me ?

arshadri commented 3 years ago

The RAMB4_S8_S8 is a dual ported memory from Xilinx. Depending on the Xilinx family/device you are mapping the design to, this name might have changed. In Xilinx you can see what the new name of this block is and rename this block to the new name. I believe it should be able to connect to that. You can also generate it from the Xilinx core generator with this name and add it to your project.

On Mon, Mar 29, 2021 at 8:53 AM kallianisawesome @.***> wrote:

I can synthesis this program in vivado2018, but I can't run implementation. It says: [DRC INBB-3] Black Box Instances:Cell 'io_ram/i1' of Type 'RAMB4_S8_S8' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully. Can sombody help me ?

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