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ashu-bitspilani / chipyard-zcu102

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Can you please write down the modification process? #1

Open Rhythmicc opened 5 months ago

Rhythmicc commented 5 months ago

As mentioned, I've updated the content related to zcu102 in the project to chipyard version 1.11.0, and then ran make SUB_PROJECT=zcu102 bitstream. It resulted in some errors, probably because of an issue with my configuration. I guess others might encounter similar issues later on. Here are the errors:

[error] /root/chipyard/fpga/fpga-shells/src/main/scala/devices/xilinx/xilinxzcu102mig/XilinxZCU102MIG.scala:6:29: object config is not a member of package freechips.rocketchip
[error] import freechips.rocketchip.config.Parameters
[error]                             ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/ip/xilinx/zcu102mig/zcu102mig.scala:7:29: object config is not a member of package freechips.rocketchip
[error] import freechips.rocketchip.config._
[error]                             ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/ip/xilinx/zcu102mig/zcu102mig.scala:6:8: object GenericParameterizedBundle is not a member of package freechips.rocketchip.util
[error] import freechips.rocketchip.util.GenericParameterizedBundle
[error]        ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/ip/xilinx/zcu102mig/zcu102mig.scala:12:46: not found: type GenericParameterizedBundle
[error] class ZCU102MIGIODDR(depth : BigInt) extends GenericParameterizedBundle(depth) {
[error]                                              ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/devices/xilinx/xilinxzcu102mig/XilinxZCU102MIG.scala:23:76: illegal inheritance; superclass ZCU102MIGIODDR
[error]  is not a subclass of the superclass Bundle
[error]  of the mixin trait ZCU102MIGIOClocksReset
[error] class XilinxZCU102MIGIO(depth : BigInt) extends ZCU102MIGIODDR(depth) with ZCU102MIGIOClocksReset
[error]                                                                            ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/devices/xilinx/xilinxzcu102mig/XilinxZCU102MIG.scala:25:68: not found: type Parameters
[error] class XilinxZCU102MIGIsland(c : XilinxZCU102MIGParams)(implicit p: Parameters) extends LazyModule with CrossesToOnlyOneClockDomain {
[error]                                                                    ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/devices/xilinx/xilinxzcu102mig/XilinxZCU102MIG.scala:25:88: could not find implicit value for parameter p: org.chipsalliance.cde.config.Parameters
[error] class XilinxZCU102MIGIsland(c : XilinxZCU102MIGParams)(implicit p: Parameters) extends LazyModule with CrossesToOnlyOneClockDomain {
[error]                                                                                        ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/ip/xilinx/zcu102mig/zcu102mig.scala:47:48: not found: type Parameters
[error] class zcu102mig(depth : BigInt)(implicit val p:Parameters) extends BlackBox
[error]                                                ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/devices/xilinx/xilinxzcu102mig/XilinxZCU102MIG.scala:137:62: not found: type Parameters
[error] class XilinxZCU102MIG(c : XilinxZCU102MIGParams)(implicit p: Parameters) extends LazyModule {
[error]                                                              ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/devices/xilinx/xilinxzcu102mig/XilinxZCU102MIG.scala:137:82: could not find implicit value for parameter p: org.chipsalliance.cde.config.Parameters
[error] class XilinxZCU102MIG(c : XilinxZCU102MIGParams)(implicit p: Parameters) extends LazyModule {
[error]                                                                                  ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/devices/xilinx/xilinxzcu102mig/XilinxZCU102MIG.scala:141:28: could not find implicit value for parameter p: org.chipsalliance.cde.config.Parameters
[error]   val buffer  = LazyModule(new TLBuffer)
[error]                            ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/devices/xilinx/xilinxzcu102mig/XilinxZCU102MIG.scala:142:28: could not find implicit value for parameter p: org.chipsalliance.cde.config.Parameters
[error] Error occurred in an application involving default arguments.
[error]   val toaxi4  = LazyModule(new TLToAXI4(adapterName = Some("mem")))
[error]                            ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/devices/xilinx/xilinxzcu102mig/XilinxZCU102MIG.scala:143:28: could not find implicit value for parameter p: org.chipsalliance.cde.config.Parameters
[error]   val indexer = LazyModule(new AXI4IdIndexer(idBits = 4))
[error]                            ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/devices/xilinx/xilinxzcu102mig/XilinxZCU102MIG.scala:144:28: could not find implicit value for parameter p: org.chipsalliance.cde.config.Parameters
[error] Error occurred in an application involving default arguments.
[error]   val deint   = LazyModule(new AXI4Deinterleaver(p(CacheBlockBytes)))
[error]                            ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/devices/xilinx/xilinxzcu102mig/XilinxZCU102MIG.scala:145:28: could not find implicit value for parameter p: org.chipsalliance.cde.config.Parameters
[error] Error occurred in an application involving default arguments.
[error]   val yank    = LazyModule(new AXI4UserYanker)
[error]                            ^
[warn] /root/chipyard/fpga/fpga-shells/src/main/scala/devices/xilinx/xilinxzcu102mig/XilinxZCU102MIG.scala:18:38: procedure syntax is deprecated for constructors: add `=`, as in method definition
[warn]   def this(c : XilinxZCU102MIGParams) {
[warn]                                      ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/devices/xilinx/xilinxzcu102mig/XilinxZCU102MIGPeriphery.scala:4:29: object config is not a member of package freechips.rocketchip
[error] import freechips.rocketchip.config._
[error]                             ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/devices/xilinx/xilinxzcu102mig/XilinxZCU102MIGPeriphery.scala:8:40: not found: type Field
[error] case object MemoryXilinxDDRKey extends Field[XilinxZCU102MIGParams]
[error]                                        ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/devices/xilinx/xilinxzcu102mig/XilinxZCU102MIGPeriphery.scala:13:58: type mismatch;
[error]  found   : sifive.fpgashells.devices.xilinx.xilinxzcu102mig.MemoryXilinxDDRKey.type
[error]  required: org.chipsalliance.cde.config.Field[?]
[error]   val xilinxzcu102mig = LazyModule(new XilinxZCU102MIG(p(MemoryXilinxDDRKey)))
[error]                                                          ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/devices/xilinx/xilinxzcu102mig/XilinxZCU102MIGPeriphery.scala:21:10: value <> is not a member of sifive.fpgashells.devices.xilinx.xilinxzcu102mig.XilinxZCU102MIGPads
[error]     pads <> xilinxzcu102mig
[error]          ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/devices/xilinx/xilinxzcu102mig/XilinxZCU102MIGPeriphery.scala:28:40: type mismatch;
[error]  found   : sifive.fpgashells.devices.xilinx.xilinxzcu102mig.MemoryXilinxDDRKey.type
[error]  required: org.chipsalliance.cde.config.Field[?]
[error]   val ranges = AddressRange.fromSets(p(MemoryXilinxDDRKey).address)
[error]                                        ^
[warn] /root/chipyard/fpga/fpga-shells/src/main/scala/devices/xilinx/xilinxzcu102mig/XilinxZCU102MIGPeriphery.scala:20:63: procedure syntax is deprecated: instead, add `: Unit =` to explicitly declare `connectXilinxZCU102MIGToPads`'s return type
[warn]   def connectXilinxZCU102MIGToPads(pads: XilinxZCU102MIGPads) {
[warn]                                                               ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/ip/xilinx/zcu102mig/zcu102mig.scala:12:73: no arguments allowed for nullary constructor Object: (): Object
[error] class ZCU102MIGIODDR(depth : BigInt) extends GenericParameterizedBundle(depth) {
[error]                                                                         ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/ip/xilinx/zcu102mig/zcu102mig.scala:51:43: illegal inheritance; superclass ZCU102MIGIODDR
[error]  is not a subclass of the superclass Bundle
[error]  of the mixin trait ZCU102MIGIOClocksReset
[error]   val io = new ZCU102MIGIODDR(depth) with ZCU102MIGIOClocksReset {
[error]                                           ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/shell/xilinx/ZCU102NewShell.scala:6:29: object config is not a member of package freechips.rocketchip
[error] import freechips.rocketchip.config._
[error]                             ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/shell/xilinx/ZCU102NewShell.scala:21:22: not found: value ClockSourceNode
[error]   val node = shell { ClockSourceNode(freqMHz = 300, jitterPS = 50)(ValName(name)) }
[error]                      ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/shell/xilinx/ZCU102NewShell.scala:21:38: not found: value freqMHz
[error]   val node = shell { ClockSourceNode(freqMHz = 300, jitterPS = 50)(ValName(name)) }
[error]                                      ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/shell/xilinx/ZCU102NewShell.scala:21:53: not found: value jitterPS
[error]   val node = shell { ClockSourceNode(freqMHz = 300, jitterPS = 50)(ValName(name)) }
[error]                                                     ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/shell/xilinx/ZCU102NewShell.scala:148:35: not found: type Field
[error] case object ZCU102DDRSize extends Field[BigInt](0x40000000L * 2) // 2GB
[error]                                   ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/shell/xilinx/ZCU102NewShell.scala:148:61: no arguments allowed for nullary constructor Object: (): Object
[error] case object ZCU102DDRSize extends Field[BigInt](0x40000000L * 2) // 2GB
[error]                                                             ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/shell/xilinx/ZCU102NewShell.scala:152:16: type mismatch;
[error]  found   : sifive.fpgashells.shell.xilinx.ZCU102DDRSize.type
[error]  required: org.chipsalliance.cde.config.Field[?]
[error]   val size = p(ZCU102DDRSize)
[error]                ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/shell/xilinx/ZCU102NewShell.scala:158:27: not found: value ClockSourceNode
[error]   val ddrUI     = shell { ClockSourceNode(freqMHz = 300) }  // Calculated as CLKOUT0 from MIG - sys_clk * DDR4_CLKFBOUT_MULT / (DDR4_CLKOUT0_DIVIDE*DDR4_DIVCLK_DIVIDE)
[error]                           ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/shell/xilinx/ZCU102NewShell.scala:158:43: not found: value freqMHz
[error]   val ddrUI     = shell { ClockSourceNode(freqMHz = 300) }  // Calculated as CLKOUT0 from MIG - sys_clk * DDR4_CLKFBOUT_MULT / (DDR4_CLKOUT0_DIVIDE*DDR4_DIVCLK_DIVIDE)
[error]                                           ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/shell/xilinx/ZCU102NewShell.scala:159:27: not found: value ClockSinkNode
[error]   val areset    = shell { ClockSinkNode(Seq(ClockSinkParameters())) }
[error]                           ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/shell/xilinx/ZCU102NewShell.scala:159:45: not found: value ClockSinkParameters
[error]   val areset    = shell { ClockSinkNode(Seq(ClockSinkParameters())) }
[error]                                             ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/shell/xilinx/ZCU102NewShell.scala:165:32: value <> is not a member of Nothing
[error]   InModuleBody { ioNode.bundle <> mig.module.io }
[error]                                ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/shell/xilinx/ZCU102NewShell.scala:236:55: not found: type Parameters
[error] abstract class ZCU102ShellBasicOverlays()(implicit p: Parameters) extends UltraScaleShell{
[error]                                                       ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/shell/xilinx/ZCU102NewShell.scala:172:33: value port is not a member of Nothing
[error]     val port = topIONode.bundle.port
[error]                                 ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/shell/xilinx/ZCU102NewShell.scala:173:8: value <> is not a member of freechips.rocketchip.diplomacy.ModuleValue[sifive.fpgashells.devices.xilinx.xilinxzcu102mig.XilinxZCU102MIGPads]
[error]     io <> port
[error]        ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/shell/xilinx/ZCU102NewShell.scala:174:8: value clock is not a member of Any
[error]     ui.clock := port.c0_ddr4_ui_clk
[error]        ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/shell/xilinx/ZCU102NewShell.scala:175:8: value reset is not a member of Any
[error]     ui.reset := /*!port.mmcm_locked ||*/ port.c0_ddr4_ui_clk_sync_rst
[error]        ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/shell/xilinx/ZCU102NewShell.scala:198:11: type mismatch;
[error]  found   : freechips.rocketchip.diplomacy.ModuleValue[sifive.fpgashells.devices.xilinx.xilinxzcu102mig.XilinxZCU102MIGPads]
[error]  required: chisel3.Data
[error] (IOPin.of(io) zip allddrpins1) foreach { case (io, pin) => shell.xdc.addPackagePin(io, pin) }
[error]           ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/shell/xilinx/ZCU102NewShell.scala:198:84: type mismatch;
[error]  found   : Any
[error]  required: sifive.fpgashells.shell.IOPin
[error] (IOPin.of(io) zip allddrpins1) foreach { case (io, pin) => shell.xdc.addPackagePin(io, pin) }
[error]                                                                                    ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/shell/xilinx/ZCU102NewShell.scala:198:88: type mismatch;
[error]  found   : Any
[error]  required: String
[error] (IOPin.of(io) zip allddrpins1) foreach { case (io, pin) => shell.xdc.addPackagePin(io, pin) }
[error]                                                                                        ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/shell/xilinx/ZCU102NewShell.scala:236:75: could not find implicit value for parameter p: org.chipsalliance.cde.config.Parameters
[error] abstract class ZCU102ShellBasicOverlays()(implicit p: Parameters) extends UltraScaleShell{
[error]                                                                           ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/shell/xilinx/ZCU102NewShell.scala:251:33: not found: type Parameters
[error] class ZCU102Shell()(implicit p: Parameters) extends ZCU102ShellBasicOverlays
[error]                                 ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/shell/xilinx/ZCU102NewShell.scala:269:16: not found: value ClockSinkNode
[error]     val sink = ClockSinkNode(Seq(ClockSinkParameters()))
[error]                ^
[error] /root/chipyard/fpga/fpga-shells/src/main/scala/shell/xilinx/ZCU102NewShell.scala:269:34: not found: value ClockSinkParameters
[error]     val sink = ClockSinkNode(Seq(ClockSinkParameters()))
[error]                                  ^
[warn] /root/chipyard/fpga/fpga-shells/src/main/scala/shell/xilinx/ZCU102NewShell.scala:168:30: Auto-application to `()` is deprecated. Supply the empty argument list `()` explicitly to invoke method get,
[warn] or remove the empty argument list from its definition (Java-defined methods are exempt).
[warn] In Scala 3, an unapplied method like this will be eta-expanded into a function.
[warn]     require (shell.sys_clock.get.isDefined, "Use of DDRZCU102Overlay depends on SysClockZCU102Overlay")
[warn]                              ^
[warn] /root/chipyard/fpga/fpga-shells/src/main/scala/shell/xilinx/ZCU102NewShell.scala:169:36: Auto-application to `()` is deprecated. Supply the empty argument list `()` explicitly to invoke method get,
[warn] or remove the empty argument list from its definition (Java-defined methods are exempt).
[warn] In Scala 3, an unapplied method like this will be eta-expanded into a function.
[warn]     val (sys, _) = shell.sys_clock.get.get.overlayOutput.node.out(0)
[warn]                                    ^
[warn] four warnings found
[error] 46 errors found
[error] (fpga_shells / Compile / compileIncremental) Compilation failed
[error] Total time: 4 s, completed Jun 18, 2024, 7:35:47 PM
make: *** [/root/chipyard/common.mk:127: /root/chipyard/.classpath_cache/chipyard.jar] Error 1
Jerryy959 commented 1 month ago

i have the same problem, could you tell me how to add the scala code: GenericParameterizedBundle