Use SCons to build gplgpu with iverilog

[kallisti5]

Just leaving this here... gplgpu could move to open source tools. It seems like quite a few things build with iverilog.

Here is an example SCons script I threw together:

verilog_simulation = Builder(
    action='iverilog -o $TARGET $VDLINCLUDES $SOURCES',
    suffix='.vvp', src_suffix='.v')

env = Environment(BUILDERS = {'GenSim' : verilog_simulation})

env['VDLINCLUDES'] = "-I ./include"

generic_sources = [
    'generic/gen_pipe.v'
]

math_sources = [
    generic_sources,
    'math/flt2int.v',
    'math/flt_add_sub.v',
    'math/flt_det.v',
    'math/flt_frac_test.v',
    'math/flt_fx_23p9.v',
    'math/flt_fx_mult.v',
    'math/flt_fx_uv.v',
    'math/flt_int.v',
    'math/flt_mult.v',
    #'math/flt_recip_orig.v',
    'math/log2_table.v',
    'math/sv_log2.v',
    'math/flt_add_sub_comb.v',
    'math/flt_alu.v',
    'math/flt_div.v',
    'math/flt_fx1616_mult.v',
    'math/flt_fx_24p8.v',
    'math/flt_fx_rnd.v',
    'math/flt_fx.v',
    'math/flt_mult_comb.v',
    'math/flt_recip_fast.v',
    #'math/flt_recip.v',
    #'math/real_log2_table.v'
]

env.GenSim('clk_gen/clk_gen.v')
env.GenSim('clk_switch/clk_switch.v')
env.GenSim('math/math', math_sources)

user@desktop hdl :) $ scons
scons: Reading SConscript files ...
scons: done reading SConscript files.
scons: Building targets ...
iverilog -o clk_gen/clk_gen.vvp -I ./include clk_gen/clk_gen.v
iverilog -o clk_switch/clk_switch.vvp -I ./include clk_switch/clk_switch.v
iverilog -o math/math.vvp -I ./include generic/gen_pipe.v math/flt2int.v math/flt_add_sub.v math/flt_det.v math/flt_frac_test.v math/flt_fx_23p9.v math/flt_fx_mult.v math/flt_fx_uv.v math/flt_int.v math/flt_mult.v math/log2_table.v math/sv_log2.v math/flt_add_sub_comb.v math/flt_alu.v math/flt_div.v math/flt_fx1616_mult.v math/flt_fx_24p8.v math/flt_fx_rnd.v math/flt_fx.v math/flt_mult_comb.v math/flt_recip_fast.v
scons: done building targets.
user@desktop hdl :) $ math/math.vvp
SORRY: math/sv_log2.v:62: $log() is not available in Icarus verilog.
user@desktop hdl :) $ 

I just wish I knew more about verilog and how these simulation files should fit together :-(

[kallisti5]

I should of understood the understandable lack of open source FPGA compilers as most of the FPGA complexity is in the vendor software. Closing as invalid for now... maybe iverilog simulations could be used but at the end of the day, we'll have to use the vendor FPGA software.