remove instruction ltr r32/m16, ltr r64/m16

[lyrachord]

Hi kobalicek: there are 3 ltr items in asmdb:

ltr"              , "R:r16/m16"                                   , "M"       , "66 0F 00 /3"                      , "ANY              Volatile PRIVILEGE=L0
ltr"              , "R:r32/m16"                                   , "M"       , "0F 00 /3"                         , "ANY              Volatile PRIVILEGE=L0
ltr"              , "R:r64/m16"                                   , "M"       , "REX.W 0F 00 /3"                   , "X64              Volatile PRIVILEGE=L0

intel manual speaks:

The operand-size attribute has no effect on this instruction. In 64-bit mode, the operand size is still fixed at 16 bits. The instruction references a 16-byte descriptor to load the 64-bit base.

AMD manual says: The operand size attribute has no effect on this instruction

I checked out it within nasm and fasm. Both report error. nasm: illegal instruction fasm: invalid size of operand.

[lyrachord]

And LLDT, LMSW, VERR, VERW as well.

ref.x86asm.net has one version of these instructions. www.sandpile.org lists Rv version, but seems sandpile have bugs.

[kobalicek]

I think you are right, I just tested it and assemblers generally refuse any form other than r16, I'm not sure why Intel is using r/m16 though - I mean this basically says you should be able to use any register, but only low 16-bits will be used.

[lyrachord]

Intel 32583 document has many errors, bu no correction in errata. I found not a few ones in my past conversion processing. I will check it out again and will try to merge it into the great asmdb.

[kobalicek]

Yeah, but here I'm sure you are right now, I tested several assemblers and none would accept any other reg than r16. I will commit a fix.

[kobalicek]

It should be fixed, please reopen if the fix is incorrect