Some errors in the generated verilog model file.

[ghost]

I am interested in the AMC, and tried it yesterday. However, it seemed that there are some errors in the verilog model file which is generated from compiler/base/verilog.py.

1. The write data (data_in) is not used in the verilog model. Instead, the internal read data "DATA" is used as write data.
2. The address (addr) is not used in the verilog model. Instead, a unknow "ADDR" is used as address.
3. In addition, the acknowlege signal of address (ack), which should be a ouptut singal, is floating.
4. Another double quotation mark is requested after the string of MEM in $display($time, "Reseting MEM); .

[sataei]

Thanks for bringing it up to our attention. I have updated the Verilog model.

[ghost]

Thanks for your quick response. Unfortunately, the new verilog model still doesn't work...

In the generated verilog model, the value of ack will be changed when one of the three "always" events occurs, but all the events are related to the edge of itself. Moreover, ack does not have an initial value. Verilog simulators, such as VCS or Questasim, will consider the initial value of ack as "X" and no "always" event will be executed, I think.

Could you give me a sample of testbench for the SRAM Verilog model for reference?

[sataei]

I have updated the Verilog model. Attached is a sample testbench for data_width = 16bit and addr_width=4bit

sram_tb.txt