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Atmel Software Package
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target/samv71: lower the PLLA multiplier #82

Closed johannesacco closed 4 years ago

johannesacco commented 4 years ago

This will lower the PLLA Clock (PLLACK) to (24+1)_12=300MHz instead of (49+1)_12=600MHz. Also change the PMC_MCKR prescaler to 1 instead of 2 which will result in the same HCLK and MCK as before this change.

This will save about 6mA during idle and also bring the PLLACK within specification (max is 500MHz according to Table 58-26, page 2055 in datasheet DS60001527B).

TonyHan11 commented 4 years ago

Hi Johannes, Thanks for your PR, it's good to save power while keeping the same performance, would you like to update the commit message to "target/samv71: lower the PLLA multiplier" and add the signed-off, thanks in advanced.

johannesacco commented 4 years ago

Hi Tony,

I have updated the commit message now.

Thanks