Always use cacheline size as alignment for dt_alloc_align

[AlynxZhou]

Apple Silicon has a larger cache line, with this we can use different size for different platforms.

Based on following darktable commits:

• https://github.com/darktable-org/darktable/commit/3b851641fcdf7ea54231f87f5f0ed72a6e238bce
• https://github.com/darktable-org/darktable/commit/0e5587112cbc2feb7dff52df1469bb82df772bdf
• https://github.com/darktable-org/darktable/commit/5a16b1ee05d1ea427bc7b38d0a30dedb67d9a52f

[sonarcloud[bot]]

Quality Gate failed

Failed conditions
5.7% Duplication on New Code (required ≤ 3%)

See analysis details on SonarCloud

[aurelienpierre]

Thanks !