avakar / usbcorev

A full-speed device-side USB peripheral core written in Verilog.
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purpose of some top-level signals #2

Open buttercutter opened 5 years ago

buttercutter commented 5 years ago

@avakar Would you be able to add some code comment / documentation on the purpose of some top-level signals ? otherwise user would need to dive into your internals of your softcore

For example, what is purpose of _usbaddress , endpoint , setup ?

module usb(
    input rst_n,
    input clk_48,

    input rx_j,
    input rx_se0,

    output tx_en,
    output tx_j,
    output tx_se0,

    input[6:0] usb_address,

    output usb_rst,

    output reg transaction_active,
    output reg[3:0] endpoint,
    output reg direction_in,
    output reg setup,
    input data_toggle,

    input[1:0] handshake,

    output reg[7:0] data_out,
    input[7:0] data_in,
    input data_in_valid,
    output reg data_strobe,
    output reg success
    );
buttercutter commented 4 years ago

@avakar why are both usb_ep_banked.v and usb_ep.v not used ?

hhchen0924 commented 3 years ago

what is purpose of usb_address , endpoint , setup ?