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avatartwo / avatar2

Python core of avatar²
Apache License 2.0
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How to deal with interrupt (NVIC) #116

Open LittleNewton opened 1 year ago

LittleNewton commented 1 year ago

Hi there.

Avatar2 worked very well when I made a software-defined peripheral and accessed it with MMIO (Memory Mapped I/O). The run trace is the same as it runs on a real board. P.S. This firmware contains no interrupt handling routine.

Nowadays, I have decided to try firmware with interrupt handling procedures. I am using the old method, a software-defined peripheral for the lack of real board. But quickly, I got a problem. NVIC, the ARM's nested vector interrupt controller, is the core of the problem.

The Definitive Guide to ARM Cortex-M3 and Cortex-M4 Processors, 3rd Edition said that NVIC-related registers could be found in the system block, which is located from 0xE000E000 to 0xE000EFFF memory range. However, when I tried to modify nvic related registers mapped to this memory range, I found the memory write operation could not realize. Is this a problem for Qemu writing not in a privileged mode?

I have been stuck on this problem for several days. Could you give me an example of how to use avatar2 to trigger an external interrupt and jump to the interrupt service routine? Thanks a lot.

rawsample commented 1 year ago

Hi!

Thanks for showing your interest in the avatar2 project. The support for interrupts is only partial, you should find a start of answer in these two replies:

albrecht-flo commented 1 year ago

@LittleNewton I am currently working on interrupt handing in Avatar2, maybe I can help you.

From your message I am assuming, you are running your firmware in QEMU without any hardware in the loop and a python peripheral to emulate the behavior of the board?

How are you accessing the NVIC registers, from the firmware itself or from Avatar2 using target.read/write_memory(...)?