Support postincrement/predecrement instructions

[dylanmckay]

The LLVM AsmParser does not take into account tokens such as + on operands as being a part of the instruction itself.

For example, this is the definition for ST P+, Rr:

// ST P+, Rr
// Stores the value of Rr into the location addressed by pointer P.
// Post increments P.
let Constraints = "$ptrreg = $base_wb,@earlyclobber $base_wb" in
def STPtrPiRr : FSTLDPtrPiReg<0b1,
                              (outs LDSTPtrReg:$base_wb),
                              (ins LDSTPtrReg:$ptrreg, GPR8:$reg, i8imm:$offs),
                              "st\t$ptrreg +, $reg",
                              [(set i16:$base_wb,
                              (post_store GPR8:$reg, i16:$ptrreg, imm:$offs))]>;

We put the + suffix on the first operand, but LLVM does not handle it correctly.

Instead, when parsing operands, we hit an "unexpected token" error.

We either need to patch the AsmParser to handle non-variable tokens like these as part of the instruction definition (and hopefully upstream!).

Either that or we could hack AVRAsmParser by manually handling all of the cases where this applies, and then passing control to the tablegen'd instruction parsing routines if this doesn't apply.

STD P+q, Rd is another offending example -- the + should be a part of instruction matching, but it isn't handled correctly.

[dylanmckay]

All instructions are now implemented, but this bug is stopping us from parsing a large subset of them.

[dylanmckay]

In commit 7798c7b, the preincrement/posdecrement parsing support was fixed.

The reg+imm operand kind (as in STD P+q, Rd) does not work currently.

[dylanmckay]

Closing as postincrement/preincrement support is finished.

Opening #71 for reg+imm parsing.